net: Introduce e1000e device emulation
This patch introduces emulation for the Intel 82574 adapter, AKA e1000e. This implementation is derived from the e1000 emulation code, and utilizes the TX/RX packet abstractions that were initially developed for the vmxnet3 device. Although some parts of the introduced code may be shared with e1000, the differences are substantial enough so that the only shared resources for the two devices are the definitions in hw/net/e1000_regs.h. Similarly to vmxnet3, the new device uses virtio headers for task offloads (for backends that support virtio extensions). Usage of virtio headers may be forcibly disabled via a boolean device property "vnet" (which is enabled by default). In such case task offloads will be performed in software, in the same way it is done on backends that do not support virtio headers. The device code is split into two parts: 1. hw/net/e1000e.c: QEMU-specific code for a network device; 2. hw/net/e1000e_core.[hc]: Device emulation according to the spec. The new device name is e1000e. Intel specifications for the 82574 controller are available at: http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf Throughput measurement results (iperf2): Fedora 22 guest, TCP, RX 4 ++------------------------------------------+ | | | X X X X X 3.5 ++ X X X X | | X | | | 3 ++ | G | X | b | | / 2.5 ++ | s | | | | 2 ++ | | | | | 1.5 X+ | | | + + + + + + + + + + + + 1 ++--+---+---+---+---+---+---+---+---+---+---+ 32 64 128 256 512 1 2 4 8 16 32 64 B B B B B KB KB KB KB KB KB KB Buffer size Fedora 22 guest, TCP, TX 18 ++-------------------------------------------+ | X | 16 ++ X X X X X | X | 14 ++ | | | 12 ++ | G | X | b 10 ++ | / | | s 8 ++ | | | 6 ++ X | | | 4 ++ | | X | 2 ++ X | X + + + + + + + + + + + 0 ++--+---+---+---+---+----+---+---+---+---+---+ 32 64 128 256 512 1 2 4 8 16 32 64 B B B B B KB KB KB KB KB KB KB Buffer size Fedora 22 guest, UDP, RX 3 ++------------------------------------------+ | X | | 2.5 ++ | | | | | 2 ++ X | G | | b | | / 1.5 ++ | s | X | | | 1 ++ | | | | X | 0.5 ++ | | X | X + + + + + 0 ++-------+--------+-------+--------+--------+ 32 64 128 256 512 1 B B B B B KB Datagram size Fedora 22 guest, UDP, TX 1 ++------------------------------------------+ | X 0.9 ++ | | | 0.8 ++ | 0.7 ++ | | | G 0.6 ++ | b | | / 0.5 ++ | s | X | 0.4 ++ | | | 0.3 ++ | 0.2 ++ X | | | 0.1 ++ X | X X + + + + 0 ++-------+--------+-------+--------+--------+ 32 64 128 256 512 1 B B B B B KB Datagram size Windows 2012R2 guest, TCP, RX 3.2 ++------------------------------------------+ | X | 3 ++ | | | 2.8 ++ | | | 2.6 ++ X | G | X X X X X b 2.4 ++ X X | / | | s 2.2 ++ | | | 2 ++ | | X X | 1.8 ++ | | | 1.6 X+ | + + + + + + + + + + + + 1.4 ++--+---+---+---+---+---+---+---+---+---+---+ 32 64 128 256 512 1 2 4 8 16 32 64 B B B B B KB KB KB KB KB KB KB Buffer size Windows 2012R2 guest, TCP, TX 14 ++-------------------------------------------+ | | | X X 12 ++ | | | 10 ++ | | | G | | b 8 ++ | / | X | s 6 ++ | | | | | 4 ++ X | | | 2 ++ | | X X X | + X X + + X X + + + + + 0 X+--+---+---+---+---+----+---+---+---+---+---+ 32 64 128 256 512 1 2 4 8 16 32 64 B B B B B KB KB KB KB KB KB KB Buffer size Windows 2012R2 guest, UDP, RX 1.6 ++------------------------------------------X | | 1.4 ++ | | | 1.2 ++ | | X | | | G 1 ++ | b | | / 0.8 ++ | s | | 0.6 ++ X | | | 0.4 ++ | | X | | | 0.2 ++ X | X + + + + + 0 ++-------+--------+-------+--------+--------+ 32 64 128 256 512 1 B B B B B KB Datagram size Windows 2012R2 guest, UDP, TX 0.6 ++------------------------------------------+ | X | | 0.5 ++ | | | | | 0.4 ++ | G | | b | | / 0.3 ++ X | s | | | | 0.2 ++ | | | | X | 0.1 ++ | | X | X X + + + + 0 ++-------+--------+-------+--------+--------+ 32 64 128 256 512 1 B B B B B KB Datagram size Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Dmitry Fleytman
Jason Wang
parent
093454e21d
commit
6f3fbe4ed0
@ -985,6 +985,11 @@ M: Dmitry Fleytman <dmitry@daynix.com>
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S: Maintained
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S: Maintained
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F: hw/net/e1000x*
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F: hw/net/e1000x*
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e1000e
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M: Dmitry Fleytman <dmitry@daynix.com>
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S: Maintained
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F: hw/net/e1000e*
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Subsystems
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Subsystems
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----------
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----------
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Audio
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Audio
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@ -18,6 +18,7 @@ CONFIG_MEGASAS_SCSI_PCI=y
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CONFIG_MPTSAS_SCSI_PCI=y
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CONFIG_MPTSAS_SCSI_PCI=y
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CONFIG_RTL8139_PCI=y
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CONFIG_RTL8139_PCI=y
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CONFIG_E1000_PCI=y
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CONFIG_E1000_PCI=y
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CONFIG_E1000E_PCI=y
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CONFIG_VMXNET3_PCI=y
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CONFIG_VMXNET3_PCI=y
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CONFIG_IDE_CORE=y
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CONFIG_IDE_CORE=y
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CONFIG_IDE_QDEV=y
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CONFIG_IDE_QDEV=y
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@ -7,6 +7,7 @@ common-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o
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common-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
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common-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
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common-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
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common-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
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common-obj-$(CONFIG_E1000_PCI) += e1000.o e1000x_common.o
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common-obj-$(CONFIG_E1000_PCI) += e1000.o e1000x_common.o
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common-obj-$(CONFIG_E1000E_PCI) += e1000e.o e1000e_core.o e1000x_common.o
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common-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
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common-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
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common-obj-$(CONFIG_VMXNET3_PCI) += net_tx_pkt.o net_rx_pkt.o
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common-obj-$(CONFIG_VMXNET3_PCI) += net_tx_pkt.o net_rx_pkt.o
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common-obj-$(CONFIG_VMXNET3_PCI) += vmxnet3.o
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common-obj-$(CONFIG_VMXNET3_PCI) += vmxnet3.o
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@ -417,6 +417,10 @@
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#define E1000_ICR_ASSERTED BIT(31)
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#define E1000_ICR_ASSERTED BIT(31)
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#define E1000_EIAC_MASK 0x01F00000
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#define E1000_EIAC_MASK 0x01F00000
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/* [TR]DBAL and [TR]DLEN masks */
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#define E1000_XDBAL_MASK (~(BIT(4) - 1))
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#define E1000_XDLEN_MASK ((BIT(20) - 1) & (~(BIT(7) - 1)))
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/* IVAR register parsing helpers */
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/* IVAR register parsing helpers */
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#define E1000_IVAR_INT_ALLOC_VALID (0x8)
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#define E1000_IVAR_INT_ALLOC_VALID (0x8)
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739
hw/net/e1000e.c
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739
hw/net/e1000e.c
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@ -0,0 +1,739 @@
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/*
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* QEMU INTEL 82574 GbE NIC emulation
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*
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* Software developer's manuals:
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* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
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*
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "net/net.h"
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#include "net/tap.h"
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#include "qemu/range.h"
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#include "sysemu/sysemu.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/net/e1000_regs.h"
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#include "e1000x_common.h"
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#include "e1000e_core.h"
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#include "trace.h"
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#define TYPE_E1000E "e1000e"
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#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
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typedef struct E1000EState {
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PCIDevice parent_obj;
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NICState *nic;
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NICConf conf;
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MemoryRegion mmio;
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MemoryRegion flash;
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MemoryRegion io;
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MemoryRegion msix;
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uint32_t ioaddr;
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uint16_t subsys_ven;
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uint16_t subsys;
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uint16_t subsys_ven_used;
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uint16_t subsys_used;
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uint32_t intr_state;
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bool disable_vnet;
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E1000ECore core;
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} E1000EState;
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#define E1000E_MMIO_IDX 0
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#define E1000E_FLASH_IDX 1
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#define E1000E_IO_IDX 2
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#define E1000E_MSIX_IDX 3
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#define E1000E_MMIO_SIZE (128 * 1024)
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#define E1000E_FLASH_SIZE (128 * 1024)
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#define E1000E_IO_SIZE (32)
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#define E1000E_MSIX_SIZE (16 * 1024)
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#define E1000E_MSIX_TABLE (0x0000)
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#define E1000E_MSIX_PBA (0x2000)
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#define E1000E_USE_MSI BIT(0)
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#define E1000E_USE_MSIX BIT(1)
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static uint64_t
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e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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E1000EState *s = opaque;
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return e1000e_core_read(&s->core, addr, size);
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}
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static void
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e1000e_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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E1000EState *s = opaque;
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e1000e_core_write(&s->core, addr, val, size);
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}
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static bool
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e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
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{
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if (s->ioaddr < 0x1FFFF) {
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*idx = s->ioaddr;
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return true;
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}
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if (s->ioaddr < 0x7FFFF) {
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trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
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return false;
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}
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if (s->ioaddr < 0xFFFFF) {
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trace_e1000e_wrn_io_addr_flash(s->ioaddr);
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return false;
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}
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trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
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return false;
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}
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static uint64_t
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e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
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{
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E1000EState *s = opaque;
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uint32_t idx;
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uint64_t val;
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switch (addr) {
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case E1000_IOADDR:
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trace_e1000e_io_read_addr(s->ioaddr);
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return s->ioaddr;
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case E1000_IODATA:
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if (e1000e_io_get_reg_index(s, &idx)) {
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val = e1000e_core_read(&s->core, idx, sizeof(val));
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trace_e1000e_io_read_data(idx, val);
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return val;
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}
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return 0;
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default:
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trace_e1000e_wrn_io_read_unknown(addr);
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return 0;
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}
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}
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static void
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e1000e_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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E1000EState *s = opaque;
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uint32_t idx;
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switch (addr) {
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case E1000_IOADDR:
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trace_e1000e_io_write_addr(val);
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s->ioaddr = (uint32_t) val;
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return;
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case E1000_IODATA:
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if (e1000e_io_get_reg_index(s, &idx)) {
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trace_e1000e_io_write_data(idx, val);
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e1000e_core_write(&s->core, idx, val, sizeof(val));
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}
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return;
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default:
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trace_e1000e_wrn_io_write_unknown(addr);
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return;
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}
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}
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static const MemoryRegionOps mmio_ops = {
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.read = e1000e_mmio_read,
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.write = e1000e_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps io_ops = {
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.read = e1000e_io_read,
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.write = e1000e_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static int
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e1000e_nc_can_receive(NetClientState *nc)
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{
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E1000EState *s = qemu_get_nic_opaque(nc);
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return e1000e_can_receive(&s->core);
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}
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static ssize_t
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e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
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{
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E1000EState *s = qemu_get_nic_opaque(nc);
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return e1000e_receive_iov(&s->core, iov, iovcnt);
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}
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static ssize_t
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e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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E1000EState *s = qemu_get_nic_opaque(nc);
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return e1000e_receive(&s->core, buf, size);
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}
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static void
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e1000e_set_link_status(NetClientState *nc)
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{
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E1000EState *s = qemu_get_nic_opaque(nc);
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e1000e_core_set_link_status(&s->core);
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}
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static NetClientInfo net_e1000e_info = {
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.type = NET_CLIENT_OPTIONS_KIND_NIC,
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.size = sizeof(NICState),
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.can_receive = e1000e_nc_can_receive,
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.receive = e1000e_nc_receive,
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.receive_iov = e1000e_nc_receive_iov,
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.link_status_changed = e1000e_set_link_status,
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};
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/*
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* EEPROM (NVM) contents documented in Table 36, section 6.1
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* and generally 6.1.2 Software accessed words.
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*/
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static const uint16_t e1000e_eeprom_template[64] = {
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/* Address | Compat. | ImVer | Compat. */
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0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
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/* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */
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0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
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/* NVM words 1,2,3 |-------------------------------|PCI-EID*/
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0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
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/* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
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0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
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/* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
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||||||
|
0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
|
||||||
|
/* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */
|
||||||
|
0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
|
||||||
|
/* SW Section */
|
||||||
|
0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
|
||||||
|
/* SW Section |CHKSUM */
|
||||||
|
0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void e1000e_core_realize(E1000EState *s)
|
||||||
|
{
|
||||||
|
s->core.owner = &s->parent_obj;
|
||||||
|
s->core.owner_nic = s->nic;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_init_msi(E1000EState *s)
|
||||||
|
{
|
||||||
|
int res;
|
||||||
|
|
||||||
|
res = msi_init(PCI_DEVICE(s),
|
||||||
|
0xD0, /* MSI capability offset */
|
||||||
|
1, /* MAC MSI interrupts */
|
||||||
|
true, /* 64-bit message addresses supported */
|
||||||
|
false); /* Per vector mask supported */
|
||||||
|
|
||||||
|
if (res > 0) {
|
||||||
|
s->intr_state |= E1000E_USE_MSI;
|
||||||
|
} else {
|
||||||
|
trace_e1000e_msi_init_fail(res);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_cleanup_msi(E1000EState *s)
|
||||||
|
{
|
||||||
|
if (s->intr_state & E1000E_USE_MSI) {
|
||||||
|
msi_uninit(PCI_DEVICE(s));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < num_vectors; i++) {
|
||||||
|
msix_vector_unuse(PCI_DEVICE(s), i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool
|
||||||
|
e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < num_vectors; i++) {
|
||||||
|
int res = msix_vector_use(PCI_DEVICE(s), i);
|
||||||
|
if (res < 0) {
|
||||||
|
trace_e1000e_msix_use_vector_fail(i, res);
|
||||||
|
e1000e_unuse_msix_vectors(s, i);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_init_msix(E1000EState *s)
|
||||||
|
{
|
||||||
|
PCIDevice *d = PCI_DEVICE(s);
|
||||||
|
int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
|
||||||
|
&s->msix,
|
||||||
|
E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
|
||||||
|
&s->msix,
|
||||||
|
E1000E_MSIX_IDX, E1000E_MSIX_PBA,
|
||||||
|
0xA0);
|
||||||
|
|
||||||
|
if (res < 0) {
|
||||||
|
trace_e1000e_msix_init_fail(res);
|
||||||
|
} else {
|
||||||
|
if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
|
||||||
|
msix_uninit(d, &s->msix, &s->msix);
|
||||||
|
} else {
|
||||||
|
s->intr_state |= E1000E_USE_MSIX;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_cleanup_msix(E1000EState *s)
|
||||||
|
{
|
||||||
|
if (s->intr_state & E1000E_USE_MSIX) {
|
||||||
|
e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
|
||||||
|
msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
|
||||||
|
{
|
||||||
|
DeviceState *dev = DEVICE(pci_dev);
|
||||||
|
NetClientState *nc;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
|
||||||
|
object_get_typename(OBJECT(s)), dev->id, s);
|
||||||
|
|
||||||
|
s->core.max_queue_num = s->conf.peers.queues - 1;
|
||||||
|
|
||||||
|
trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
|
||||||
|
memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
|
||||||
|
|
||||||
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
|
||||||
|
|
||||||
|
/* Setup virtio headers */
|
||||||
|
if (s->disable_vnet) {
|
||||||
|
s->core.has_vnet = false;
|
||||||
|
trace_e1000e_cfg_support_virtio(false);
|
||||||
|
return;
|
||||||
|
} else {
|
||||||
|
s->core.has_vnet = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < s->conf.peers.queues; i++) {
|
||||||
|
nc = qemu_get_subqueue(s->nic, i);
|
||||||
|
if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
|
||||||
|
s->core.has_vnet = false;
|
||||||
|
trace_e1000e_cfg_support_virtio(false);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
trace_e1000e_cfg_support_virtio(true);
|
||||||
|
|
||||||
|
for (i = 0; i < s->conf.peers.queues; i++) {
|
||||||
|
nc = qemu_get_subqueue(s->nic, i);
|
||||||
|
qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
|
||||||
|
qemu_using_vnet_hdr(nc->peer, true);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint64_t
|
||||||
|
e1000e_gen_dsn(uint8_t *mac)
|
||||||
|
{
|
||||||
|
return (uint64_t)(mac[5]) |
|
||||||
|
(uint64_t)(mac[4]) << 8 |
|
||||||
|
(uint64_t)(mac[3]) << 16 |
|
||||||
|
(uint64_t)(0x00FF) << 24 |
|
||||||
|
(uint64_t)(0x00FF) << 32 |
|
||||||
|
(uint64_t)(mac[2]) << 40 |
|
||||||
|
(uint64_t)(mac[1]) << 48 |
|
||||||
|
(uint64_t)(mac[0]) << 56;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
|
||||||
|
{
|
||||||
|
int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
|
||||||
|
|
||||||
|
if (ret >= 0) {
|
||||||
|
pci_set_word(pdev->config + offset + PCI_PM_PMC,
|
||||||
|
PCI_PM_CAP_VER_1_1 |
|
||||||
|
pmc);
|
||||||
|
|
||||||
|
pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
|
||||||
|
PCI_PM_CTRL_STATE_MASK |
|
||||||
|
PCI_PM_CTRL_PME_ENABLE |
|
||||||
|
PCI_PM_CTRL_DATA_SEL_MASK);
|
||||||
|
|
||||||
|
pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
|
||||||
|
PCI_PM_CTRL_PME_STATUS);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
|
||||||
|
uint32_t val, int len)
|
||||||
|
{
|
||||||
|
E1000EState *s = E1000E(pci_dev);
|
||||||
|
|
||||||
|
pci_default_write_config(pci_dev, address, val, len);
|
||||||
|
|
||||||
|
if (range_covers_byte(address, len, PCI_COMMAND) &&
|
||||||
|
(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
|
||||||
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
|
||||||
|
{
|
||||||
|
static const uint16_t e1000e_pmrb_offset = 0x0C8;
|
||||||
|
static const uint16_t e1000e_pcie_offset = 0x0E0;
|
||||||
|
static const uint16_t e1000e_aer_offset = 0x100;
|
||||||
|
static const uint16_t e1000e_dsn_offset = 0x140;
|
||||||
|
E1000EState *s = E1000E(pci_dev);
|
||||||
|
uint8_t *macaddr;
|
||||||
|
|
||||||
|
trace_e1000e_cb_pci_realize();
|
||||||
|
|
||||||
|
pci_dev->config_write = e1000e_write_config;
|
||||||
|
|
||||||
|
pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
|
||||||
|
pci_dev->config[PCI_INTERRUPT_PIN] = 1;
|
||||||
|
|
||||||
|
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
|
||||||
|
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
|
||||||
|
|
||||||
|
s->subsys_ven_used = s->subsys_ven;
|
||||||
|
s->subsys_used = s->subsys;
|
||||||
|
|
||||||
|
/* Define IO/MMIO regions */
|
||||||
|
memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
|
||||||
|
"e1000e-mmio", E1000E_MMIO_SIZE);
|
||||||
|
pci_register_bar(pci_dev, E1000E_MMIO_IDX,
|
||||||
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We provide a dummy implementation for the flash BAR
|
||||||
|
* for drivers that may theoretically probe for its presence.
|
||||||
|
*/
|
||||||
|
memory_region_init(&s->flash, OBJECT(s),
|
||||||
|
"e1000e-flash", E1000E_FLASH_SIZE);
|
||||||
|
pci_register_bar(pci_dev, E1000E_FLASH_IDX,
|
||||||
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
|
||||||
|
|
||||||
|
memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
|
||||||
|
"e1000e-io", E1000E_IO_SIZE);
|
||||||
|
pci_register_bar(pci_dev, E1000E_IO_IDX,
|
||||||
|
PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
||||||
|
|
||||||
|
memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
|
||||||
|
E1000E_MSIX_SIZE);
|
||||||
|
pci_register_bar(pci_dev, E1000E_MSIX_IDX,
|
||||||
|
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
|
||||||
|
|
||||||
|
/* Create networking backend */
|
||||||
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
||||||
|
macaddr = s->conf.macaddr.a;
|
||||||
|
|
||||||
|
e1000e_init_msix(s);
|
||||||
|
|
||||||
|
if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
|
||||||
|
hw_error("Failed to initialize PCIe capability");
|
||||||
|
}
|
||||||
|
|
||||||
|
e1000e_init_msi(s);
|
||||||
|
|
||||||
|
if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
|
||||||
|
PCI_PM_CAP_DSI) < 0) {
|
||||||
|
hw_error("Failed to initialize PM capability");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) {
|
||||||
|
hw_error("Failed to initialize AER capability");
|
||||||
|
}
|
||||||
|
|
||||||
|
pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
|
||||||
|
e1000e_gen_dsn(macaddr));
|
||||||
|
|
||||||
|
e1000e_init_net_peer(s, pci_dev, macaddr);
|
||||||
|
|
||||||
|
/* Initialize core */
|
||||||
|
e1000e_core_realize(s);
|
||||||
|
|
||||||
|
e1000e_core_pci_realize(&s->core,
|
||||||
|
e1000e_eeprom_template,
|
||||||
|
sizeof(e1000e_eeprom_template),
|
||||||
|
macaddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_pci_uninit(PCIDevice *pci_dev)
|
||||||
|
{
|
||||||
|
E1000EState *s = E1000E(pci_dev);
|
||||||
|
|
||||||
|
trace_e1000e_cb_pci_uninit();
|
||||||
|
|
||||||
|
e1000e_core_pci_uninit(&s->core);
|
||||||
|
|
||||||
|
pcie_aer_exit(pci_dev);
|
||||||
|
pcie_cap_exit(pci_dev);
|
||||||
|
|
||||||
|
qemu_del_nic(s->nic);
|
||||||
|
|
||||||
|
e1000e_cleanup_msix(s);
|
||||||
|
e1000e_cleanup_msi(s);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_qdev_reset(DeviceState *dev)
|
||||||
|
{
|
||||||
|
E1000EState *s = E1000E(dev);
|
||||||
|
|
||||||
|
trace_e1000e_cb_qdev_reset();
|
||||||
|
|
||||||
|
e1000e_core_reset(&s->core);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_pre_save(void *opaque)
|
||||||
|
{
|
||||||
|
E1000EState *s = opaque;
|
||||||
|
|
||||||
|
trace_e1000e_cb_pre_save();
|
||||||
|
|
||||||
|
e1000e_core_pre_save(&s->core);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int e1000e_post_load(void *opaque, int version_id)
|
||||||
|
{
|
||||||
|
E1000EState *s = opaque;
|
||||||
|
|
||||||
|
trace_e1000e_cb_post_load();
|
||||||
|
|
||||||
|
if ((s->subsys != s->subsys_used) ||
|
||||||
|
(s->subsys_ven != s->subsys_ven_used)) {
|
||||||
|
fprintf(stderr,
|
||||||
|
"ERROR: Cannot migrate while device properties "
|
||||||
|
"(subsys/subsys_ven) differ");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return e1000e_core_post_load(&s->core);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription e1000e_vmstate_tx = {
|
||||||
|
.name = "e1000e-tx",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT8(props.sum_needed, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT8(props.tucss, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT8(props.tucso, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT16(props.tucse, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT16(props.mss, struct e1000e_tx),
|
||||||
|
VMSTATE_UINT32(props.paylen, struct e1000e_tx),
|
||||||
|
VMSTATE_INT8(props.ip, struct e1000e_tx),
|
||||||
|
VMSTATE_INT8(props.tcp, struct e1000e_tx),
|
||||||
|
VMSTATE_BOOL(props.tse, struct e1000e_tx),
|
||||||
|
VMSTATE_BOOL(props.cptse, struct e1000e_tx),
|
||||||
|
VMSTATE_BOOL(skip_cp, struct e1000e_tx),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const VMStateDescription e1000e_vmstate_intr_timer = {
|
||||||
|
.name = "e1000e-intr-timer",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
|
||||||
|
VMSTATE_BOOL(running, E1000IntrDelayTimer),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
#define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \
|
||||||
|
VMSTATE_STRUCT(_f, _s, 0, \
|
||||||
|
e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
|
||||||
|
|
||||||
|
#define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \
|
||||||
|
VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \
|
||||||
|
e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
|
||||||
|
|
||||||
|
static const VMStateDescription e1000e_vmstate = {
|
||||||
|
.name = "e1000e",
|
||||||
|
.version_id = 1,
|
||||||
|
.minimum_version_id = 1,
|
||||||
|
.pre_save = e1000e_pre_save,
|
||||||
|
.post_load = e1000e_post_load,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_PCIE_DEVICE(parent_obj, E1000EState),
|
||||||
|
VMSTATE_MSIX(parent_obj, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_UINT32(ioaddr, E1000EState),
|
||||||
|
VMSTATE_UINT32(intr_state, E1000EState),
|
||||||
|
VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
|
||||||
|
VMSTATE_UINT8(core.rx_desc_len, E1000EState),
|
||||||
|
VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
|
||||||
|
E1000_PSRCTL_BUFFS_PER_DESC),
|
||||||
|
VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
|
||||||
|
VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
|
||||||
|
VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
|
||||||
|
E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
|
||||||
|
VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
|
||||||
|
VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
|
||||||
|
|
||||||
|
VMSTATE_UINT32(core.delayed_causes, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_UINT16(subsys, E1000EState),
|
||||||
|
VMSTATE_UINT16(subsys_ven, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
|
||||||
|
VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
|
||||||
|
E1000E_MSIX_VEC_NUM),
|
||||||
|
VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
|
||||||
|
E1000E_MSIX_VEC_NUM),
|
||||||
|
|
||||||
|
VMSTATE_UINT32(core.itr_guest_value, E1000EState),
|
||||||
|
VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
|
||||||
|
E1000E_MSIX_VEC_NUM),
|
||||||
|
|
||||||
|
VMSTATE_UINT16(core.vet, E1000EState),
|
||||||
|
|
||||||
|
VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
|
||||||
|
e1000e_vmstate_tx, struct e1000e_tx),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static PropertyInfo e1000e_prop_disable_vnet,
|
||||||
|
e1000e_prop_subsys_ven,
|
||||||
|
e1000e_prop_subsys;
|
||||||
|
|
||||||
|
static Property e1000e_properties[] = {
|
||||||
|
DEFINE_NIC_PROPERTIES(E1000EState, conf),
|
||||||
|
DEFINE_PROP_DEFAULT("disable_vnet_hdr", E1000EState, disable_vnet, false,
|
||||||
|
e1000e_prop_disable_vnet, bool),
|
||||||
|
DEFINE_PROP_DEFAULT("subsys_ven", E1000EState, subsys_ven,
|
||||||
|
PCI_VENDOR_ID_INTEL,
|
||||||
|
e1000e_prop_subsys_ven, uint16_t),
|
||||||
|
DEFINE_PROP_DEFAULT("subsys", E1000EState, subsys, 0,
|
||||||
|
e1000e_prop_subsys, uint16_t),
|
||||||
|
DEFINE_PROP_END_OF_LIST(),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void e1000e_class_init(ObjectClass *class, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(class);
|
||||||
|
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
|
||||||
|
|
||||||
|
c->realize = e1000e_pci_realize;
|
||||||
|
c->exit = e1000e_pci_uninit;
|
||||||
|
c->vendor_id = PCI_VENDOR_ID_INTEL;
|
||||||
|
c->device_id = E1000_DEV_ID_82574L;
|
||||||
|
c->revision = 0;
|
||||||
|
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
|
||||||
|
c->is_express = 1;
|
||||||
|
|
||||||
|
dc->desc = "Intel 82574L GbE Controller";
|
||||||
|
dc->reset = e1000e_qdev_reset;
|
||||||
|
dc->vmsd = &e1000e_vmstate;
|
||||||
|
dc->props = e1000e_properties;
|
||||||
|
|
||||||
|
e1000e_prop_disable_vnet = qdev_prop_uint8;
|
||||||
|
e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
|
||||||
|
"perform SW offloads emulation "
|
||||||
|
"instead";
|
||||||
|
|
||||||
|
e1000e_prop_subsys_ven = qdev_prop_uint16;
|
||||||
|
e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
|
||||||
|
|
||||||
|
e1000e_prop_subsys = qdev_prop_uint16;
|
||||||
|
e1000e_prop_subsys.description = "PCI device Subsystem ID";
|
||||||
|
|
||||||
|
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void e1000e_instance_init(Object *obj)
|
||||||
|
{
|
||||||
|
E1000EState *s = E1000E(obj);
|
||||||
|
device_add_bootindex_property(obj, &s->conf.bootindex,
|
||||||
|
"bootindex", "/ethernet-phy@0",
|
||||||
|
DEVICE(obj), NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo e1000e_info = {
|
||||||
|
.name = TYPE_E1000E,
|
||||||
|
.parent = TYPE_PCI_DEVICE,
|
||||||
|
.instance_size = sizeof(E1000EState),
|
||||||
|
.class_init = e1000e_class_init,
|
||||||
|
.instance_init = e1000e_instance_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void e1000e_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&e1000e_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(e1000e_register_types)
|
||||||
3476
hw/net/e1000e_core.c
Normal file
3476
hw/net/e1000e_core.c
Normal file
File diff suppressed because it is too large
Load Diff
146
hw/net/e1000e_core.h
Normal file
146
hw/net/e1000e_core.h
Normal file
@ -0,0 +1,146 @@
|
|||||||
|
/*
|
||||||
|
* Core code for QEMU e1000e emulation
|
||||||
|
*
|
||||||
|
* Software developer's manuals:
|
||||||
|
* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
|
||||||
|
*
|
||||||
|
* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
|
||||||
|
* Developed by Daynix Computing LTD (http://www.daynix.com)
|
||||||
|
*
|
||||||
|
* Authors:
|
||||||
|
* Dmitry Fleytman <dmitry@daynix.com>
|
||||||
|
* Leonid Bloch <leonid@daynix.com>
|
||||||
|
* Yan Vugenfirer <yan@daynix.com>
|
||||||
|
*
|
||||||
|
* Based on work done by:
|
||||||
|
* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
|
||||||
|
* Copyright (c) 2008 Qumranet
|
||||||
|
* Based on work done by:
|
||||||
|
* Copyright (c) 2007 Dan Aloni
|
||||||
|
* Copyright (c) 2004 Antony T Curtis
|
||||||
|
*
|
||||||
|
* This library is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU Lesser General Public
|
||||||
|
* License as published by the Free Software Foundation; either
|
||||||
|
* version 2 of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||||
|
* Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public
|
||||||
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define E1000E_PHY_PAGE_SIZE (0x20)
|
||||||
|
#define E1000E_PHY_PAGES (0x07)
|
||||||
|
#define E1000E_MAC_SIZE (0x8000)
|
||||||
|
#define E1000E_EEPROM_SIZE (64)
|
||||||
|
#define E1000E_MSIX_VEC_NUM (5)
|
||||||
|
#define E1000E_NUM_QUEUES (2)
|
||||||
|
|
||||||
|
typedef struct E1000Core E1000ECore;
|
||||||
|
|
||||||
|
enum { PHY_R = BIT(0),
|
||||||
|
PHY_W = BIT(1),
|
||||||
|
PHY_RW = PHY_R | PHY_W,
|
||||||
|
PHY_ANYPAGE = BIT(2) };
|
||||||
|
|
||||||
|
typedef struct E1000IntrDelayTimer_st {
|
||||||
|
QEMUTimer *timer;
|
||||||
|
bool running;
|
||||||
|
uint32_t delay_reg;
|
||||||
|
uint32_t delay_resolution_ns;
|
||||||
|
E1000ECore *core;
|
||||||
|
} E1000IntrDelayTimer;
|
||||||
|
|
||||||
|
struct E1000Core {
|
||||||
|
uint32_t mac[E1000E_MAC_SIZE];
|
||||||
|
uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];
|
||||||
|
uint16_t eeprom[E1000E_EEPROM_SIZE];
|
||||||
|
|
||||||
|
uint32_t rxbuf_sizes[E1000_PSRCTL_BUFFS_PER_DESC];
|
||||||
|
uint32_t rx_desc_buf_size;
|
||||||
|
uint32_t rxbuf_min_shift;
|
||||||
|
uint8_t rx_desc_len;
|
||||||
|
|
||||||
|
QEMUTimer *autoneg_timer;
|
||||||
|
|
||||||
|
struct e1000e_tx {
|
||||||
|
e1000x_txd_props props;
|
||||||
|
|
||||||
|
bool skip_cp;
|
||||||
|
struct NetTxPkt *tx_pkt;
|
||||||
|
} tx[E1000E_NUM_QUEUES];
|
||||||
|
|
||||||
|
struct NetRxPkt *rx_pkt;
|
||||||
|
|
||||||
|
bool has_vnet;
|
||||||
|
int max_queue_num;
|
||||||
|
|
||||||
|
/* Interrupt moderation management */
|
||||||
|
uint32_t delayed_causes;
|
||||||
|
|
||||||
|
E1000IntrDelayTimer radv;
|
||||||
|
E1000IntrDelayTimer rdtr;
|
||||||
|
E1000IntrDelayTimer raid;
|
||||||
|
|
||||||
|
E1000IntrDelayTimer tadv;
|
||||||
|
E1000IntrDelayTimer tidv;
|
||||||
|
|
||||||
|
E1000IntrDelayTimer itr;
|
||||||
|
bool itr_intr_pending;
|
||||||
|
|
||||||
|
E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM];
|
||||||
|
bool eitr_intr_pending[E1000E_MSIX_VEC_NUM];
|
||||||
|
|
||||||
|
VMChangeStateEntry *vmstate;
|
||||||
|
|
||||||
|
uint32_t itr_guest_value;
|
||||||
|
uint32_t eitr_guest_value[E1000E_MSIX_VEC_NUM];
|
||||||
|
|
||||||
|
uint16_t vet;
|
||||||
|
|
||||||
|
uint8_t permanent_mac[ETH_ALEN];
|
||||||
|
|
||||||
|
NICState *owner_nic;
|
||||||
|
PCIDevice *owner;
|
||||||
|
void (*owner_start_recv)(PCIDevice *d);
|
||||||
|
};
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size);
|
||||||
|
|
||||||
|
uint64_t
|
||||||
|
e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_pci_realize(E1000ECore *regs,
|
||||||
|
const uint16_t *eeprom_templ,
|
||||||
|
uint32_t eeprom_size,
|
||||||
|
const uint8_t *macaddr);
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_reset(E1000ECore *core);
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_pre_save(E1000ECore *core);
|
||||||
|
|
||||||
|
int
|
||||||
|
e1000e_core_post_load(E1000ECore *core);
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_set_link_status(E1000ECore *core);
|
||||||
|
|
||||||
|
void
|
||||||
|
e1000e_core_pci_uninit(E1000ECore *core);
|
||||||
|
|
||||||
|
int
|
||||||
|
e1000e_can_receive(E1000ECore *core);
|
||||||
|
|
||||||
|
ssize_t
|
||||||
|
e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size);
|
||||||
|
|
||||||
|
ssize_t
|
||||||
|
e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt);
|
||||||
160
trace-events
160
trace-events
@ -1967,3 +1967,163 @@ e1000x_rx_oversized(size_t size) "Received packet dropped because it was oversiz
|
|||||||
e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x"
|
e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x"
|
||||||
e1000x_link_negotiation_start(void) "Start link auto negotiation"
|
e1000x_link_negotiation_start(void) "Start link auto negotiation"
|
||||||
e1000x_link_negotiation_done(void) "Auto negotiation is completed"
|
e1000x_link_negotiation_done(void) "Auto negotiation is completed"
|
||||||
|
|
||||||
|
# hw/net/e1000e_core.c
|
||||||
|
e1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
|
||||||
|
e1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
|
||||||
|
e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x"
|
||||||
|
e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED"
|
||||||
|
e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x"
|
||||||
|
e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED"
|
||||||
|
e1000e_core_eeeprom_write(uint16_t bit_in, uint16_t bit_out, uint16_t reading) "eeprom bitnum in %d out %d, reading %d"
|
||||||
|
e1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X"
|
||||||
|
e1000e_core_ctrl_sw_reset(void) "Doing SW reset"
|
||||||
|
e1000e_core_ctrl_phy_reset(void) "Doing PHY reset"
|
||||||
|
|
||||||
|
e1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d"
|
||||||
|
e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d"
|
||||||
|
e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d"
|
||||||
|
e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d"
|
||||||
|
e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d"
|
||||||
|
e1000e_link_status_changed(bool status) "New link status: %d"
|
||||||
|
|
||||||
|
e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
|
||||||
|
e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
|
||||||
|
e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)"
|
||||||
|
e1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented."
|
||||||
|
e1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented."
|
||||||
|
e1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported"
|
||||||
|
e1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported"
|
||||||
|
e1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported"
|
||||||
|
e1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported"
|
||||||
|
e1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported"
|
||||||
|
|
||||||
|
e1000e_tx_disabled(void) "TX Disabled"
|
||||||
|
e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x"
|
||||||
|
|
||||||
|
e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u"
|
||||||
|
|
||||||
|
e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full"
|
||||||
|
e1000e_rx_can_recv(void) "Can receive"
|
||||||
|
e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u"
|
||||||
|
e1000e_rx_null_descriptor(void) "Null RX descriptor!!"
|
||||||
|
e1000e_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X"
|
||||||
|
e1000e_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X"
|
||||||
|
e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]"
|
||||||
|
e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]"
|
||||||
|
e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]"
|
||||||
|
e1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u"
|
||||||
|
e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
|
||||||
|
e1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u"
|
||||||
|
e1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x"
|
||||||
|
e1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments"
|
||||||
|
e1000e_rx_packet_size(size_t full, size_t vhdr, size_t data) "Received packet of %zu bytes total, %zu virt header, %zu data"
|
||||||
|
e1000e_rx_flt_dropped(void) "Received packet dropped by RX filter"
|
||||||
|
e1000e_rx_written_to_guest(uint32_t causes) "Received packet written to guest (ICR causes %u)"
|
||||||
|
e1000e_rx_not_written_to_guest(uint32_t causes) "Received packet NOT written to guest (ICR causes %u)"
|
||||||
|
e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)"
|
||||||
|
e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)"
|
||||||
|
e1000e_rx_set_cso(int cso_state) "RX CSO state set to %d"
|
||||||
|
e1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u"
|
||||||
|
e1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X"
|
||||||
|
e1000e_rx_start_recv(void)
|
||||||
|
|
||||||
|
e1000e_rx_rss_started(void) "Starting RSS processing"
|
||||||
|
e1000e_rx_rss_disabled(void) "RSS is disabled"
|
||||||
|
e1000e_rx_rss_type(uint32_t type) "RSS type is %u"
|
||||||
|
e1000e_rx_rss_ip4(bool isfragment, bool istcp, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: fragment %d, tcp %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d"
|
||||||
|
e1000e_rx_rss_ip6(uint32_t rfctl, bool ex_dis, bool new_ex_dis, bool istcp, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: rfctl 0x%X, ex_dis: %d, new_ex_dis: %d, tcp %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6 enabled %d, ipv6ex enabled %d, ipv6 enabled %d"
|
||||||
|
e1000e_rx_rss_dispatched_to_queue(int queue_idx) "Packet being dispatched to queue %d"
|
||||||
|
|
||||||
|
e1000e_rx_metadata_protocols(bool isip4, bool isip6, bool isudp, bool istcp) "protocols: ip4: %d, ip6: %d, udp: %d, tcp: %d"
|
||||||
|
e1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X"
|
||||||
|
e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X"
|
||||||
|
e1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X"
|
||||||
|
e1000e_rx_metadata_ack(void) "the packet is TCP ACK"
|
||||||
|
e1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u"
|
||||||
|
e1000e_rx_metadata_no_virthdr(void) "the packet has no virt-header"
|
||||||
|
e1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info"
|
||||||
|
e1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled"
|
||||||
|
e1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled"
|
||||||
|
e1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum"
|
||||||
|
e1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum"
|
||||||
|
e1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X"
|
||||||
|
e1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL"
|
||||||
|
e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL"
|
||||||
|
|
||||||
|
e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X"
|
||||||
|
|
||||||
|
e1000e_irq_set_cause(uint32_t cause) "IRQ cause set 0x%x"
|
||||||
|
e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x"
|
||||||
|
e1000e_irq_throttling_no_pending_interrupts(void) "No pending interrupts to notify"
|
||||||
|
e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR"
|
||||||
|
e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR"
|
||||||
|
e1000e_irq_throttling_no_pending_vec(int idx) "No pending interrupts for vector %d"
|
||||||
|
e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]"
|
||||||
|
e1000e_irq_msix_notify(uint32_t cause) "MSI-X notify 0x%x"
|
||||||
|
e1000e_irq_legacy_notify(bool level) "IRQ line state: %d"
|
||||||
|
e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x"
|
||||||
|
e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x"
|
||||||
|
e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x"
|
||||||
|
e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x"
|
||||||
|
e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x"
|
||||||
|
e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x"
|
||||||
|
e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)"
|
||||||
|
e1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ cause 0x%x, ICR: 0x%x"
|
||||||
|
e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x"
|
||||||
|
e1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing ICR bits 0x%x: 0x%x --> 0x%x"
|
||||||
|
e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x"
|
||||||
|
e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME"
|
||||||
|
e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x"
|
||||||
|
e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x"
|
||||||
|
e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x"
|
||||||
|
e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x"
|
||||||
|
e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
|
||||||
|
e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME"
|
||||||
|
e1000e_irq_ims_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X"
|
||||||
|
e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X"
|
||||||
|
e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x"
|
||||||
|
e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts"
|
||||||
|
e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns"
|
||||||
|
e1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X"
|
||||||
|
e1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running"
|
||||||
|
e1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running"
|
||||||
|
e1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running"
|
||||||
|
e1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running"
|
||||||
|
e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u"
|
||||||
|
e1000e_irq_itr_set(uint32_t val) "ITR = %u"
|
||||||
|
e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)"
|
||||||
|
e1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging delayed causes 0x%X to ICR 0x%X"
|
||||||
|
e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u"
|
||||||
|
|
||||||
|
e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x"
|
||||||
|
e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x"
|
||||||
|
|
||||||
|
e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x"
|
||||||
|
e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x"
|
||||||
|
|
||||||
|
# hw/net/e1000e.c
|
||||||
|
e1000e_cb_pci_realize(void) "E1000E PCI realize entry"
|
||||||
|
e1000e_cb_pci_uninit(void) "E1000E PCI unit entry"
|
||||||
|
e1000e_cb_qdev_reset(void) "E1000E qdev reset entry"
|
||||||
|
e1000e_cb_pre_save(void) "E1000E pre save entry"
|
||||||
|
e1000e_cb_post_load(void) "E1000E post load entry"
|
||||||
|
|
||||||
|
e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64
|
||||||
|
e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64
|
||||||
|
e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64
|
||||||
|
e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64
|
||||||
|
e1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64
|
||||||
|
e1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64
|
||||||
|
e1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64
|
||||||
|
e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented"
|
||||||
|
e1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64
|
||||||
|
|
||||||
|
e1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d"
|
||||||
|
e1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d"
|
||||||
|
e1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d"
|
||||||
|
|
||||||
|
e1000e_cfg_support_virtio(bool support) "Virtio header supported: %d"
|
||||||
|
|
||||||
|
e1000e_vm_state_running(void) "VM state is running"
|
||||||
|
e1000e_vm_state_stopped(void) "VM state is stopped"
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user