mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

aspeed: add the definitions for the AST2400 A1 SoC

Browse Source 
There is not much differences with the A0 revision apart from the DDR
calibration.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2016-12-27 14:59:28 +00:00 committed by Peter Maydell
parent 74af4eec29
commit 6efbac908f
4 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
hw/arm/aspeed_soc.c
View File

@ -58,6 +58,16 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spi_bases = aspeed_soc_ast2400_spi_bases, .spi_bases = aspeed_soc_ast2400_spi_bases,
.fmc_typename = "aspeed.smc.fmc", .fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames, .spi_typename = aspeed_soc_ast2400_typenames,
}, {
.name = "ast2400-a1",
.cpu_model = "arm926",
.silicon_rev = AST2400_A1_SILICON_REV,
.sdram_base = AST2400_SDRAM_BASE,
.sram_size = 0x8000,
.spis_num = 1,
.spi_bases = aspeed_soc_ast2400_spi_bases,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
}, { }, {
.name = "ast2400", .name = "ast2400",
.cpu_model = "arm926", .cpu_model = "arm926",

2
hw/misc/aspeed_scu.c
View File

@ -231,6 +231,7 @@ static void aspeed_scu_reset(DeviceState *dev)
switch (s->silicon_rev) { switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV: case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
reset = ast2400_a0_resets; reset = ast2400_a0_resets;
break; break;
case AST2500_A0_SILICON_REV: case AST2500_A0_SILICON_REV:
@ -249,6 +250,7 @@ static void aspeed_scu_reset(DeviceState *dev)
static uint32_t aspeed_silicon_revs[] = { static uint32_t aspeed_silicon_revs[] = {
AST2400_A0_SILICON_REV, AST2400_A0_SILICON_REV,
AST2400_A1_SILICON_REV,
AST2500_A0_SILICON_REV, AST2500_A0_SILICON_REV,
AST2500_A1_SILICON_REV, AST2500_A1_SILICON_REV,
}; };

3
hw/misc/aspeed_sdmc.c
View File

@ -119,6 +119,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
/* Make sure readonly bits are kept */ /* Make sure readonly bits are kept */
switch (s->silicon_rev) { switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV: case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
data &= ~ASPEED_SDMC_READONLY_MASK; data &= ~ASPEED_SDMC_READONLY_MASK;
break; break;
case AST2500_A0_SILICON_REV: case AST2500_A0_SILICON_REV:
@ -193,6 +194,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
/* Set ram size bit and defaults values */ /* Set ram size bit and defaults values */
switch (s->silicon_rev) { switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV: case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
s->regs[R_CONF] |= s->regs[R_CONF] |=
ASPEED_SDMC_VGA_COMPAT | ASPEED_SDMC_VGA_COMPAT |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits); ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
@ -224,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
switch (s->silicon_rev) { switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV: case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
s->ram_bits = ast2400_rambits(s); s->ram_bits = ast2400_rambits(s);
break; break;
case AST2500_A0_SILICON_REV: case AST2500_A0_SILICON_REV:

1
include/hw/misc/aspeed_scu.h
View File

@ -32,6 +32,7 @@ typedef struct AspeedSCUState {
} AspeedSCUState; } AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U #define AST2400_A0_SILICON_REV 0x02000303U
#define AST2400_A1_SILICON_REV 0x02010303U
#define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A0_SILICON_REV 0x04000303U
#define AST2500_A1_SILICON_REV 0x04010303U #define AST2500_A1_SILICON_REV 0x04010303U