tcg/ppc: Update vector support for v3.00 load/store
These new instructions are a mix of those like LXSD that are only conditional only on MSR.VEC and those like LXV that are conditional on MSR.VEC for TX=1. Thus, in the end, we can consider all of these as Altivec instructions. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -471,11 +471,16 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
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#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
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#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
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#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
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#define LXSD (OPCD(57) | 2) /* v3.00 */
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#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
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#define STVX XO31(231)
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#define STVEWX XO31(199)
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#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
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#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
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#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
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#define STXSD (OPCD(61) | 2) /* v3.00 */
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#define VADDSBS VX4(768)
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#define VADDUBS VX4(512)
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@ -1114,7 +1119,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
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TCGReg base, tcg_target_long offset)
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{
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tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
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bool is_store = false;
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bool is_int_store = false;
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TCGReg rs = TCG_REG_TMP1;
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switch (opi) {
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@ -1127,11 +1132,19 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
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break;
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}
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break;
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case LXSD:
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case STXSD:
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align = 3;
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break;
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case LXV:
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case STXV:
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align = 15;
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break;
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case STD:
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align = 3;
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/* FALLTHRU */
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case STB: case STH: case STW:
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is_store = true;
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is_int_store = true;
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break;
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}
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@ -1140,7 +1153,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
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if (rs == base) {
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rs = TCG_REG_R0;
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}
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tcg_debug_assert(!is_store || rs != rt);
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tcg_debug_assert(!is_int_store || rs != rt);
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tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
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tcg_out32(s, opx | TAB(rt & 31, base, rs));
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return;
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@ -1205,7 +1218,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
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case TCG_TYPE_V64:
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tcg_debug_assert(ret >= TCG_REG_V0);
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if (have_vsx) {
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tcg_out_mem_long(s, 0, LXSDX, ret, base, offset);
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tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
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ret, base, offset);
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break;
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}
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tcg_debug_assert((offset & 7) == 0);
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@ -1217,7 +1231,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
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case TCG_TYPE_V128:
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tcg_debug_assert(ret >= TCG_REG_V0);
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tcg_debug_assert((offset & 15) == 0);
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tcg_out_mem_long(s, 0, LVX, ret, base, offset);
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tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
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LVX, ret, base, offset);
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break;
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default:
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g_assert_not_reached();
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@ -1258,7 +1273,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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case TCG_TYPE_V64:
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tcg_debug_assert(arg >= TCG_REG_V0);
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if (have_vsx) {
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tcg_out_mem_long(s, 0, STXSDX, arg, base, offset);
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tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
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STXSDX, arg, base, offset);
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break;
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}
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tcg_debug_assert((offset & 7) == 0);
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@ -1271,7 +1287,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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break;
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case TCG_TYPE_V128:
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tcg_debug_assert(arg >= TCG_REG_V0);
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tcg_out_mem_long(s, 0, STVX, arg, base, offset);
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tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
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STVX, arg, base, offset);
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break;
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default:
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g_assert_not_reached();
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@ -3042,7 +3059,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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tcg_debug_assert(out >= TCG_REG_V0);
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switch (vece) {
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case MO_8:
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if (have_isa_3_00) {
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tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
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} else {
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tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
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}
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elt = extract32(offset, 0, 4);
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#ifndef HOST_WORDS_BIGENDIAN
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elt ^= 15;
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@ -3051,7 +3072,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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break;
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case MO_16:
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tcg_debug_assert((offset & 1) == 0);
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if (have_isa_3_00) {
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tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
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} else {
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tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
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}
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elt = extract32(offset, 1, 3);
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#ifndef HOST_WORDS_BIGENDIAN
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elt ^= 7;
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@ -3059,6 +3084,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
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break;
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case MO_32:
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if (have_isa_3_00) {
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tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
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break;
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}
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tcg_debug_assert((offset & 3) == 0);
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tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
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elt = extract32(offset, 2, 2);
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