tests/tcg/tricore: Add LD.BU tests
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-11-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -13,6 +13,7 @@ TESTS += test_fmul.tst
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TESTS += test_ftoi.tst
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TESTS += test_imask.tst
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TESTS += test_insert.tst
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TESTS += test_ld_bu.tst
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TESTS += test_madd.tst
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TESTS += test_msub.tst
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TESTS += test_muls.tst
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@ -4,6 +4,10 @@
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movh DREG_TEMP_LI, up:val; \
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or reg, reg, DREG_TEMP_LI; \
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#define LIA(reg, val) \
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LI(DREG_TEMP, val) \
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mov.a reg, DREG_TEMP;
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/* Address definitions */
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#define TESTDEV_ADDR 0xf0000000
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/* Register definitions */
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@ -18,6 +22,10 @@
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#define DREG_TEST_NUM %d14
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#define DREG_CORRECT_RESULT %d15
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#define AREG_ADDR %a0
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#define AREG_CORRECT_RESULT %a3
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#define MEM_BASE_ADDR 0xd0000000
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#define DREG_DEV_ADDR %a15
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#define EREG_RS1 %e6
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@ -60,11 +68,24 @@ test_ ## num: \
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mov DREG_TEST_NUM, num; \
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jne DREG_CALC_PSW, DREG_CORRECT_PSW, fail;
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#define TEST_LD(insn, num, result, addr_result, ld_pattern) \
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test_ ## num: \
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LIA(AREG_ADDR, test_data) \
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insn DREG_CALC_RESULT, ld_pattern; \
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LI(DREG_CORRECT_RESULT, result) \
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mov DREG_TEST_NUM, num; \
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jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail; \
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mov.d DREG_CALC_RESULT, AREG_ADDR; \
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LI(DREG_CORRECT_RESULT, addr_result) \
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jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
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/* Actual test case type
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* e.g inst %dX, %dY -> TEST_D_D
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* inst %dX, %dY, %dZ -> TEST_D_DD
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* inst %eX, %dY, %dZ -> TEST_E_DD
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*/
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#define TEST_D_D(insn, num, result, rs1) \
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TEST_CASE(num, DREG_CALC_RESULT, result, \
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LI(DREG_RS1, rs1); \
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@ -143,6 +164,8 @@ test_ ## num: \
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insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2); \
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)
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/* Pass/Fail handling part */
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#define TEST_PASSFAIL \
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j pass; \
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15
tests/tcg/tricore/test_ld_bu.S
Normal file
15
tests/tcg/tricore/test_ld_bu.S
Normal file
@ -0,0 +1,15 @@
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#include "macros.h"
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.data
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test_data:
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.word 0xaffedead
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.word 0x001122ff
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.text
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.global _start
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_start:
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# expect. addr reg val after load
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# insn num expect. load value | pattern for loading
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# | | | | |
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TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
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TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
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TEST_PASSFAIL
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