target/arm: Enable FEAT_DGH for -cpu max
This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -17,6 +17,7 @@ the following architecture extensions:
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- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
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- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
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- FEAT_CSV3 (Cache speculation variant 3)
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- FEAT_DGH (Data gathering hint)
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- FEAT_DIT (Data Independent Timing instructions)
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- FEAT_DPB (DC CVAP instruction)
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- FEAT_Debugv8p2 (Debug changes for v8.2)
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@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
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t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
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t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
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t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
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cpu->isar.id_aa64isar1 = t;
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@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t insn,
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break;
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case 0b00100: /* SEV */
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case 0b00101: /* SEVL */
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case 0b00110: /* DGH */
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/* we treat all as NOP at least for now */
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break;
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case 0b00111: /* XPACLRI */
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