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target/arm: Enable FEAT_DGH for -cpu max

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This extension concerns not merging memory access, which TCG does
not implement.  Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 13:02:40 -05:00 committed by Peter Maydell
parent 3082b86b10
commit 6d9650191a
3 changed files with 3 additions and 0 deletions
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1
docs/system/arm/emulation.rst
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@ -17,6 +17,7 @@ the following architecture extensions:
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
- FEAT_CSV3 (Cache speculation variant 3) - FEAT_CSV3 (Cache speculation variant 3)
- FEAT_DGH (Data gathering hint)
- FEAT_DIT (Data Independent Timing instructions) - FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction) - FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_Debugv8p2 (Debug changes for v8.2)

1
target/arm/cpu64.c
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@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
cpu->isar.id_aa64isar1 = t; cpu->isar.id_aa64isar1 = t;

1
target/arm/translate-a64.c
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@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t insn,
break; break;
case 0b00100: /* SEV */ case 0b00100: /* SEV */
case 0b00101: /* SEVL */ case 0b00101: /* SEVL */
case 0b00110: /* DGH */
/* we treat all as NOP at least for now */ /* we treat all as NOP at least for now */
break; break;
case 0b00111: /* XPACLRI */ case 0b00111: /* XPACLRI */