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CPU specific boot mode (Robert Reif)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3542 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-11-07 17:03:37 +00:00
parent bc4edd79ee
commit 6d5f237a59
5 changed files with 15 additions and 10 deletions
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6
cpu-exec.c
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@ -181,10 +181,8 @@ static inline TranslationBlock *tb_find_fast(void)
flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
| (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
#else #else
// FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor // FPU enable . Supervisor
flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3) flags = (env->psref << 4) | env->psrs;
| ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
| env->psrs;
#endif #endif
cs_base = env->npc; cs_base = env->npc;
pc = env->pc; pc = env->pc;

2
target-sparc/cpu.h
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@ -147,7 +147,6 @@
/* MMU */ /* MMU */
#define MMU_E (1<<0) #define MMU_E (1<<0)
#define MMU_NF (1<<1) #define MMU_NF (1<<1)
#define MMU_BM (1<<14)
#define PTE_ENTRYTYPE_MASK 3 #define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK 0x1c #define PTE_ACCESS_MASK 0x1c
@ -200,6 +199,7 @@ typedef struct CPUSPARCState {
int interrupt_index; int interrupt_index;
int interrupt_request; int interrupt_request;
int halted; int halted;
uint32_t mmu_bm;
/* NOTE: we allow 8 more registers to handle wrapping */ /* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8]; target_ulong regbase[NWINDOWS * 16 + 8];

2
target-sparc/helper.c
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@ -114,7 +114,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
// Boot mode: instruction fetches are taken from PROM // Boot mode: instruction fetches are taken from PROM
if (rw == 2 && (env->mmuregs[0] & MMU_BM)) { if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
*physical = 0xff0000000ULL | (address & 0x3ffffULL); *physical = 0xff0000000ULL | (address & 0x3ffffULL);
*prot = PAGE_READ | PAGE_EXEC; *prot = PAGE_READ | PAGE_EXEC;
return 0; return 0;

4
target-sparc/op_helper.c
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@ -493,8 +493,8 @@ void helper_st_asi(int asi, int size)
oldreg = env->mmuregs[reg]; oldreg = env->mmuregs[reg];
switch(reg) { switch(reg) {
case 0: case 0:
env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
// Mappings generated during no-fault mode or MMU // Mappings generated during no-fault mode or MMU
// disabled mode are invalid in normal mode // disabled mode are invalid in normal mode
if (oldreg != env->mmuregs[reg]) if (oldreg != env->mmuregs[reg])

11
target-sparc/translate.c
View File

@ -59,6 +59,7 @@ struct sparc_def_t {
target_ulong iu_version; target_ulong iu_version;
uint32_t fpu_version; uint32_t fpu_version;
uint32_t mmu_version; uint32_t mmu_version;
uint32_t mmu_bm;
}; };
static uint16_t *gen_opc_ptr; static uint16_t *gen_opc_ptr;
@ -3482,7 +3483,7 @@ void cpu_reset(CPUSPARCState *env)
#else #else
env->pc = 0; env->pc = 0;
env->mmuregs[0] &= ~(MMU_E | MMU_NF); env->mmuregs[0] &= ~(MMU_E | MMU_NF);
env->mmuregs[0] |= MMU_BM; env->mmuregs[0] |= env->mmu_bm;
#endif #endif
env->npc = env->pc + 4; env->npc = env->pc + 4;
#endif #endif
@ -3496,7 +3497,6 @@ CPUSPARCState *cpu_sparc_init(void)
if (!env) if (!env)
return NULL; return NULL;
cpu_exec_init(env); cpu_exec_init(env);
cpu_reset(env);
return (env); return (env);
} }
@ -3515,30 +3515,35 @@ static const sparc_def_t sparc_defs[] = {
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
.mmu_bm = 0x00004000,
}, },
{ {
.name = "Fujitsu MB86907", .name = "Fujitsu MB86907",
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
.mmu_bm = 0x00004000,
}, },
{ {
.name = "TI MicroSparc I", .name = "TI MicroSparc I",
.iu_version = 0x41000000, .iu_version = 0x41000000,
.fpu_version = 4 << 17, .fpu_version = 4 << 17,
.mmu_version = 0x41000000, .mmu_version = 0x41000000,
.mmu_bm = 0x00004000,
}, },
{ {
.name = "TI SuperSparc II", .name = "TI SuperSparc II",
.iu_version = 0x40000000, .iu_version = 0x40000000,
.fpu_version = 0 << 17, .fpu_version = 0 << 17,
.mmu_version = 0x04000000, .mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
}, },
{ {
.name = "Ross RT620", .name = "Ross RT620",
.iu_version = 0x1e000000, .iu_version = 0x1e000000,
.fpu_version = 1 << 17, .fpu_version = 1 << 17,
.mmu_version = 0x17000000, .mmu_version = 0x17000000,
.mmu_bm = 0x00004000,
}, },
#endif #endif
}; };
@ -3579,9 +3584,11 @@ int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, unsigned int
env->version = def->iu_version; env->version = def->iu_version;
env->fsr = def->fpu_version; env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64) #if !defined(TARGET_SPARC64)
env->mmu_bm = def->mmu_bm;
env->mmuregs[0] |= def->mmu_version; env->mmuregs[0] |= def->mmu_version;
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
#endif #endif
cpu_reset(env);
return 0; return 0;
} }