From b78aae9bb65876baa47b73d5cf63372171630bf9 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 01/11] hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding to a given sid. The function extracts both the PCIe bus number and the devfn to return this data. Current computation of devfn is wrong as it only returns the PCIe function instead of slot | function. Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data") Signed-off-by: Eric Auger Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 2 +- include/hw/arm/smmu-common.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3098915d07..55c75d65d2 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -351,7 +351,7 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid) bus_n = PCI_BUS_NUM(sid); smmu_bus = smmu_find_smmu_pcibus(s, bus_n); if (smmu_bus) { - devfn = sid & 0x7; + devfn = SMMU_PCI_DEVFN(sid); smmu = smmu_bus->pbdev[devfn]; if (smmu) { return &smmu->iommu; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 50e2912a95..b07cadd0ef 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -24,6 +24,7 @@ #define SMMU_PCI_BUS_MAX 256 #define SMMU_PCI_DEVFN_MAX 256 +#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) #define SMMU_MAX_VA_BITS 48 From 086ede32afc9c70de3d75c4fb91c63db790cbd5c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 02/11] ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option The CMSDK timer behaviour is that an interrupt is triggered when the counter counts down from 1 to 0; however one is not triggered if the counter is manually set to 0 by a guest write to the counter register. Currently ptimer can't handle this; add a policy option to allow a ptimer user to request this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Message-id: 20180703171044.9503-2-peter.maydell@linaro.org --- hw/core/ptimer.c | 22 +++++++++++++++++++++- include/hw/ptimer.h | 9 +++++++++ tests/ptimer-test.c | 25 +++++++++++++++++++------ 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 7221c68a98..170fd34d8b 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -45,8 +45,20 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust) uint32_t period_frac = s->period_frac; uint64_t period = s->period; uint64_t delta = s->delta; + bool suppress_trigger = false; - if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { + /* + * Note that if delta_adjust is 0 then we must be here because of + * a count register write or timer start, not because of timer expiry. + * In that case the policy might require us to suppress the timer trigger + * that we would otherwise generate for a zero delta. + */ + if (delta_adjust == 0 && + (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { + suppress_trigger = true; + } + if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) + && !suppress_trigger) { ptimer_trigger(s); } @@ -353,6 +365,14 @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) s->bh = bh; s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); s->policy_mask = policy_mask; + + /* + * These two policies are incompatible -- trigger-on-decrement implies + * a timer trigger when the count becomes 0, but no-immediate-trigger + * implies a trigger when the count stops being 0. + */ + assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && + (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); return s; } diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index fc4ef5cc1d..0731d9aef1 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -69,6 +69,15 @@ * not the one less. */ #define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4) +/* + * Starting to run with a zero counter, or setting the counter to "0" via + * ptimer_set_count() or ptimer_set_limit() will not trigger the timer + * (though it will cause a reload). Only a counter decrement to "0" + * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; + * ptimer_init() will assert() that you don't set both. + */ +#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) + /* ptimer.c */ typedef struct ptimer_state ptimer_state; typedef void (*ptimer_cb)(void *opaque); diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c index 41488896f7..b30aad0737 100644 --- a/tests/ptimer-test.c +++ b/tests/ptimer-test.c @@ -208,6 +208,7 @@ static void check_periodic(gconstpointer arg) bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); triggered = false; @@ -311,7 +312,7 @@ static void check_periodic(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_immediate_reload ? 0 : 10); - if (no_immediate_trigger) { + if (no_immediate_trigger || trig_only_on_dec) { g_assert_false(triggered); } else { g_assert_true(triggered); @@ -506,6 +507,7 @@ static void check_run_with_delta_0(gconstpointer arg) bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); triggered = false; @@ -515,7 +517,7 @@ static void check_run_with_delta_0(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_immediate_reload ? 0 : 99); - if (no_immediate_trigger) { + if (no_immediate_trigger || trig_only_on_dec) { g_assert_false(triggered); } else { g_assert_true(triggered); @@ -563,7 +565,7 @@ static void check_run_with_delta_0(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_immediate_reload ? 0 : 99); - if (no_immediate_trigger) { + if (no_immediate_trigger || trig_only_on_dec) { g_assert_false(triggered); } else { g_assert_true(triggered); @@ -609,6 +611,7 @@ static void check_periodic_with_load_0(gconstpointer arg) ptimer_state *ptimer = ptimer_init(bh, *policy); bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER); bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); + bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); triggered = false; @@ -617,7 +620,7 @@ static void check_periodic_with_load_0(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); - if (no_immediate_trigger) { + if (no_immediate_trigger || trig_only_on_dec) { g_assert_false(triggered); } else { g_assert_true(triggered); @@ -667,6 +670,7 @@ static void check_oneshot_with_load_0(gconstpointer arg) QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); ptimer_state *ptimer = ptimer_init(bh, *policy); bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); + bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); triggered = false; @@ -675,7 +679,7 @@ static void check_oneshot_with_load_0(gconstpointer arg) g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); - if (no_immediate_trigger) { + if (no_immediate_trigger || trig_only_on_dec) { g_assert_false(triggered); } else { g_assert_true(triggered); @@ -725,6 +729,10 @@ static void add_ptimer_tests(uint8_t policy) g_strlcat(policy_name, "no_counter_rounddown,", 256); } + if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) { + g_strlcat(policy_name, "trigger_only_on_decrement,", 256); + } + g_test_add_data_func_full( tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name), g_memdup(&policy, 1), check_set_count, g_free); @@ -790,10 +798,15 @@ static void add_ptimer_tests(uint8_t policy) static void add_all_ptimer_policies_comb_tests(void) { - int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN; + int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT; int policy = PTIMER_POLICY_DEFAULT; for (; policy < (last_policy << 1); policy++) { + if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && + (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { + /* Incompatible policy flag settings -- don't try to test them */ + continue; + } add_ptimer_tests(policy); } } From 6583080ed87ea218acae59f1c52b7b11ffec240d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 03/11] hw/timer/cmsdk-apb-timer: Correct ptimer policy settings The CMSDK timer interrupt triggers when the counter goes from 1 to 0, so we want to trigger immediately, rather than waiting for a clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting. We also do not want to get an interrupt if the guest sets the counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT policy. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Message-id: 20180703171044.9503-3-peter.maydell@linaro.org --- hw/timer/cmsdk-apb-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index 9878746609..1f99081db1 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -201,7 +201,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) bh = qemu_bh_new(cmsdk_apb_timer_tick, s); s->timer = ptimer_init(bh, PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | - PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | + PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); From 0e256833085cc9d292e59a5bda9b886fd09a5f83 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 04/11] hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode The CMSDK APB timer is currently always configured as periodic timer. This results in the following messages when trying to boot Linux. Timer with delta zero, disabling If the timer limit set with the RELOAD command is 0, the timer needs to be enabled as one-shot timer. Signed-off-by: Guenter Roeck Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Guenter Roeck Signed-off-by: Peter Maydell --- hw/timer/cmsdk-apb-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index 1f99081db1..3ebdc7be40 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -119,7 +119,7 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, } s->ctrl = value & 0xf; if (s->ctrl & R_CTRL_EN_MASK) { - ptimer_run(s->timer, 0); + ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); } else { ptimer_stop(s->timer); } From 1a9b30646edd8d10caaa9727611750bf57d08c74 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 05/11] hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE If the CMSDK APB timer is set up with a zero RELOAD value then it will count down to zero, fire once and then stay at zero. From the point of view of the ptimer system, the timer is disabled; but the enable bit in the CTRL register is still set and if the guest subsequently writes to the RELOAD or VALUE registers this should cause the timer to start counting down again. Add code to the write paths for RELOAD and VALUE so that we correctly restart the timer in this situation. Conversely, if the new RELOAD and VALUE are both zero, we should stop the ptimer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Message-id: 20180703171044.9503-5-peter.maydell@linaro.org --- hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index 3ebdc7be40..801d1dba74 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -126,10 +126,26 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, break; case A_RELOAD: /* Writing to reload also sets the current timer value */ + if (!value) { + ptimer_stop(s->timer); + } ptimer_set_limit(s->timer, value, 1); + if (value && (s->ctrl & R_CTRL_EN_MASK)) { + /* + * Make sure timer is running (it might have stopped if this + * was an expired one-shot timer) + */ + ptimer_run(s->timer, 0); + } break; case A_VALUE: + if (!value && !ptimer_get_limit(s->timer)) { + ptimer_stop(s->timer); + } ptimer_set_count(s->timer, value); + if (value && (s->ctrl & R_CTRL_EN_MASK)) { + ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); + } break; case A_INTSTATUS: /* Just one bit, which is W1C. */ From 2f95a3b09aebdcb5c9152a7ac434a5d57441fe82 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 06/11] target/arm: Suppress Coverity warning for PRF These instructions must perform the sve_access_check, but since they are implemented as NOPs there is no generated code to elide when the access check fails. Fixes: Coverity issues 1393780 & 1393779. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c080345b9c..d41f1155f9 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5164,7 +5164,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn) static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn) { /* Prefetch is a nop within QEMU. */ - sve_access_check(s); + (void)sve_access_check(s); return true; } @@ -5174,7 +5174,7 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn) return false; } /* Prefetch is a nop within QEMU. */ - sve_access_check(s); + (void)sve_access_check(s); return true; } From 499748d7683198a765d17b4fdf6901ab9dca920c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 07/11] tcg: Restrict check_size_impl to multiples of the line size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Normally this is automatic in the size restrictions that are placed on vector sizes coming from the implementation. However, for the legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final 24 bytes of the vector register. Without this check, do_dup selects TCG_TYPE_V128 and clears only 16 bytes. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: 20180705191929.30773-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tcg/tcg-op-gvec.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 22db1590d5..61c25f5784 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -287,8 +287,11 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, in units of LNSZ. This limits the expansion of inline code. */ static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) { - uint32_t lnct = oprsz / lnsz; - return lnct >= 1 && lnct <= MAX_UNROLL; + if (oprsz % lnsz == 0) { + uint32_t lnct = oprsz / lnsz; + return lnct >= 1 && lnct <= MAX_UNROLL; + } + return false; } static void expand_clr(uint32_t dofs, uint32_t maxsz); From 973558a3f869e591d2406dd8226ec0c4e32a3c3e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 08/11] target/arm: Fix do_predset for large VL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use MAKE_64BIT_MASK instead of open-coding. Remove an odd vector size check that is unlikely to be more profitable than 3 64-bit integer stores. Correct the iteration for WORD to avoid writing too much data. Fixes RISU tests of PTRUE for VL 256. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: 20180705191929.30773-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d41f1155f9..374051cd20 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1438,7 +1438,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) setsz = numelem << esz; lastword = word = pred_esz_masks[esz]; if (setsz % 64) { - lastword &= ~(-1ull << (setsz % 64)); + lastword &= MAKE_64BIT_MASK(0, setsz % 64); } } @@ -1457,19 +1457,13 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); goto done; } - if (oprsz * 8 == setsz + 8) { - tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); - tcg_gen_movi_i64(t, 0); - tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8); - goto done; - } } setsz /= 8; fullsz /= 8; tcg_gen_movi_i64(t, word); - for (i = 0; i < setsz; i += 8) { + for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) { tcg_gen_st_i64(t, cpu_env, ofs + i); } if (lastword != word) { From 7abf56eed13a2338b8d3eda60e0d3c4e490a663f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 09/11] hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DeviceClass::reset models a "cold power-on" reset which can also be used to powercycle a device; but there is no "hot reset" (a.k.a. soft-reset) method available. The OMAP MMC Power-Up Control bit is not designed to powercycle a card, but to disable it without powering it off (pseudo-reset): Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A] MMC_CON[11] Power-Up Control (POW) This bit must be set to 1 before any valid transaction to either MMC/SD or SPI memory cards. When 1, the card is considered powered-up and the controller core is enabled. When 0, the card is considered powered-down (system dependent), and the controller core logic is in pseudo-reset state. This is, the MMC_STAT flags and the FIFO pointers are reset, any access to MMC_DATA[DATA] has no effect, a write into the MMC.CMD register is ignored, and a setting of MMC_SPI[STR] to 1 is ignored. By splitting the 'pseudo-reset' code out of the 'power-on' reset function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i recently exposed by ecd219f7abb. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20180706162155.8432-2-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/sd/omap_mmc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 671264b650..d0c98ca021 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -1,6 +1,8 @@ /* * OMAP on-chip MMC/SD host emulation. * + * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A) + * * Copyright (C) 2006-2007 Andrzej Zaborowski * * This program is free software; you can redistribute it and/or @@ -278,6 +280,12 @@ static void omap_mmc_update(void *opaque) omap_mmc_interrupts_update(s); } +static void omap_mmc_pseudo_reset(struct omap_mmc_s *host) +{ + host->status = 0; + host->fifo_len = 0; +} + void omap_mmc_reset(struct omap_mmc_s *host) { host->last_cmd = 0; @@ -286,11 +294,9 @@ void omap_mmc_reset(struct omap_mmc_s *host) host->dw = 0; host->mode = 0; host->enable = 0; - host->status = 0; host->mask = 0; host->cto = 0; host->dto = 0; - host->fifo_len = 0; host->blen = 0; host->blen_counter = 0; host->nblk = 0; @@ -305,6 +311,8 @@ void omap_mmc_reset(struct omap_mmc_s *host) qemu_set_irq(host->coverswitch, host->cdet_state); host->clkdiv = 0; + omap_mmc_pseudo_reset(host); + /* Since we're still using the legacy SD API the card is not plugged * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. @@ -459,7 +467,7 @@ static void omap_mmc_write(void *opaque, hwaddr offset, if (s->dw != 0 && s->lines < 4) printf("4-bit SD bus enabled\n"); if (!s->enable) - omap_mmc_reset(s); + omap_mmc_pseudo_reset(s); break; case 0x10: /* MMC_STAT */ From 5bd366b467fd23d0530580573b2024d3962222c3 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 9 Jul 2018 14:51:34 +0100 Subject: [PATCH 10/11] boards.h: Remove doc comment reference to nonexistent function commit b08199c6fbea1 accidentally added a reference to a doc comment to a nonexistent memory_region_allocate_aux_memory(). This was a leftover from a previous version of the patchset which defined memory_region_allocate_aux_memory() for "allocate RAM MemoryRegion and register it for migration" and left "memory_region_init_ram()" with its original semantics of "allocate RAM MR but do not register for migration". In the end we decided on the approach of "memory_region_init_ram() registers the MR for migration, and memory_region_init_ram_nomigrate() is a new function which does not", but this comment change got left in by mistake. Revert that part of the commit. Reported-by: Thomas Huth Signed-off-by: Peter Maydell Message-id: 20180702130605.13611-1-peter.maydell@linaro.org --- include/hw/boards.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 79069ddcbe..d139a431a6 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -35,8 +35,7 @@ * * Smaller pieces of memory (display RAM, static RAMs, etc) don't need * to be backed via the -mem-path memory backend and can simply - * be created via memory_region_allocate_aux_memory() or - * memory_region_init_ram(). + * be created via memory_region_init_ram(). */ void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, const char *name, From 8fad0a65582c0a6e324580f45516461e9b6aa439 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 9 Jul 2018 14:51:35 +0100 Subject: [PATCH 11/11] hw/net/dp8393x: don't make prom region 'nomigrate' Currently we use memory_region_init_rom_nomigrate() to create the "dp3893x-prom" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that this is a a cross-version migration compatibility break for the MIPS "magnum" and "pica61" machines. Signed-off-by: Peter Maydell Reviewed-by: Aleksandar Markovic Message-id: 20180706174309.27110-1-peter.maydell@linaro.org --- hw/net/dp8393x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index f2d2ce344c..b53fcaa8bc 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -887,7 +887,7 @@ static void dp8393x_realize(DeviceState *dev, Error **errp) s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ - memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev), + memory_region_init_ram(&s->prom, OBJECT(dev), "dp8393x-prom", SONIC_PROM_SIZE, &local_err); if (local_err) { error_propagate(errp, local_err);