mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw/char/stm32l4x5_usart.c: Enable USART ACK bit response

Browse Source 
SW modifying USART_CR1 TE bit should cuase HW to respond by altering
USART_ISR TEACK bit, and likewise for RE and REACK bit.

This resolves some but not all issues necessary for the official STM USART
HAL driver to function as is.

Fixes: 87b77e6e01 ("hw/char/stm32l4x5_usart: Enable serial read and write")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540
Signed-off-by: Jacob Abrams <satur9nine@gmail.com>
Message-id: 20240911043255.51966-1-satur9nine@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jacob Abrams 2024-09-10 21:32:55 -07:00 committed by Peter Maydell
parent f21b07e272
commit 6cce0dcc6f
2 changed files with 51 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
hw/char/stm32l4x5_usart.c
View File

@ -154,6 +154,21 @@ REG32(RDR, 0x24)
REG32(TDR, 0x28)
FIELD(TDR, TDR, 0, 9)
static void stm32l4x5_update_isr(Stm32l4x5UsartBaseState *s)
{
if (s->cr1 & R_CR1_TE_MASK) {
s->isr |= R_ISR_TEACK_MASK;
} else {
s->isr &= ~R_ISR_TEACK_MASK;
}
if (s->cr1 & R_CR1_RE_MASK) {
s->isr |= R_ISR_REACK_MASK;
} else {
s->isr &= ~R_ISR_REACK_MASK;
}
}
static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s)
{
if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) ||
@ -456,6 +471,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
case A_CR1:
s->cr1 = value;
stm32l4x5_update_params(s);
stm32l4x5_update_isr(s);
stm32l4x5_update_irq(s);
return;
case A_CR2:

36
tests/qtest/stm32l4x5_usart-test.c
View File

@ -36,6 +36,8 @@ REG32(GTPR, 0x10)
REG32(RTOR, 0x14)
REG32(RQR, 0x18)
REG32(ISR, 0x1C)
FIELD(ISR, REACK, 22, 1)
FIELD(ISR, TEACK, 21, 1)
FIELD(ISR, TXE, 7, 1)
FIELD(ISR, RXNE, 5, 1)
FIELD(ISR, ORE, 3, 1)
@ -191,7 +193,7 @@ static void init_uart(QTestState *qts)
/* Enable the transmitter, the receiver and the USART. */
qtest_writel(qts, (USART1_BASE_ADDR + A_CR1),
R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK);
cr1 | R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK);
}
static void test_write_read(void)
@ -298,6 +300,37 @@ static void test_send_str(void)
qtest_quit(qts);
}
static void test_ack(void)
{
uint32_t cr1;
uint32_t isr;
QTestState *qts = qtest_init("-M b-l475e-iot01a");
init_uart(qts);
cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1));
/* Disable the transmitter and receiver. */
qtest_writel(qts, (USART1_BASE_ADDR + A_CR1),
cr1 & ~(R_CR1_RE_MASK | R_CR1_TE_MASK));
/* Test ISR ACK for transmitter and receiver disabled */
isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR));
g_assert_false(isr & R_ISR_TEACK_MASK);
g_assert_false(isr & R_ISR_REACK_MASK);
/* Enable the transmitter and receiver. */
qtest_writel(qts, (USART1_BASE_ADDR + A_CR1),
cr1 | (R_CR1_RE_MASK | R_CR1_TE_MASK));
/* Test ISR ACK for transmitter and receiver disabled */
isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR));
g_assert_true(isr & R_ISR_TEACK_MASK);
g_assert_true(isr & R_ISR_REACK_MASK);
qtest_quit(qts);
}
int main(int argc, char **argv)
{
int ret;
@ -310,6 +343,7 @@ int main(int argc, char **argv)
qtest_add_func("stm32l4x5/usart/send_char", test_send_char);
qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str);
qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
qtest_add_func("stm32l4x5/usart/ack", test_ack);
ret = g_test_run();
return ret;