disas/riscv: Add amocas.[w,d,q] instructions
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231207153842.32401-3-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -903,6 +903,9 @@ typedef enum {
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rv_op_vwsll_vv = 872,
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rv_op_vwsll_vx = 873,
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rv_op_vwsll_vi = 874,
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rv_op_amocas_w = 875,
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rv_op_amocas_d = 876,
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rv_op_amocas_q = 877,
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} rv_op;
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/* register names */
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@ -2090,6 +2093,9 @@ const rv_opcode_data rvi_opcode_data[] = {
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{ "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
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{ "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
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{ "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
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{ "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
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{ "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
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{ "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
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};
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/* CSR names */
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@ -2841,6 +2847,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 34: op = rv_op_amoxor_w; break;
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case 35: op = rv_op_amoxor_d; break;
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case 36: op = rv_op_amoxor_q; break;
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case 42: op = rv_op_amocas_w; break;
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case 43: op = rv_op_amocas_d; break;
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case 44: op = rv_op_amocas_q; break;
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case 66: op = rv_op_amoor_w; break;
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case 67: op = rv_op_amoor_d; break;
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case 68: op = rv_op_amoor_q; break;
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