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target/mips: Define R5900 MMI2 opcode constants

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Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Fredrik Noring 2018-10-21 17:34:21 +02:00 committed by Aleksandar Markovic
parent 7759654112
commit 6c03ef6aaa
1 changed files with 48 additions and 0 deletions
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48
target/mips/translate.c
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@ -2275,6 +2275,54 @@ enum {
TX79_MMI1_QFSRV = (0x1B << 6) | TX79_MMI_CLASS_MMI1,
};
/*
* TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI2:
*
* 31 26 10 6 5 0
* +--------+----------------------+--------+--------+
* | MMI | |function| MMI2 |
* +--------+----------------------+--------+--------+
*
* function bits 7..6
* bits | 0 | 1 | 2 | 3
* 10..8 | 00 | 01 | 10 | 11
* -------+-------+-------+-------+-------
* 0 000 | PMADDW| * | PSLLVW| PSRLVW
* 1 001 | PMSUBW| * | * | *
* 2 010 | PMFHI | PMFLO | PINTH | *
* 3 011 | PMULTW| PDIVW | PCPYLD| *
* 4 100 | PMADDH| PHMADH| PAND | PXOR
* 5 101 | PMSUBH| PHMSBH| * | *
* 6 110 | * | * | PEXEH | PREVH
* 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
*/
#define MASK_TX79_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
enum {
TX79_MMI2_PMADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PSLLVW = (0x02 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PSRLVW = (0x03 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMSUBW = (0x04 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMFHI = (0x08 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMFLO = (0x09 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PINTH = (0x0A << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMULTW = (0x0C << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PDIVW = (0x0D << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PCPYLD = (0x0E << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMADDH = (0x10 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PHMADH = (0x11 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PAND = (0x12 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PXOR = (0x13 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMSUBH = (0x14 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PHMSBH = (0x15 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PEXEH = (0x1A << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PREVH = (0x1B << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMULTH = (0x1C << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PDIVBW = (0x1D << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PEXEW = (0x1E << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,
};
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];