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disas: cris: QOMify target specific disas setup

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Move the target_disas() cris specifics to the QOM disas_set_info() hook
and delete the cris specific code in disas.c.

This also now adds support for monitor_disas() to cris.

E.g.
(qemu) xp 0x40004000
0000000040004000: 0x1e6f25f0

And before this patch:
(qemu) xp/i 0x40004000
0x40004000: Asm output not supported on this arch

After:
(qemu) xp/i 0x40004000
0x40004000:  di
(qemu) xp/i 0x40004002
0x40004002:  move.d 0xb003c004,$r1

Note: second example is 6-byte misaligned instruction!

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Crosthwaite 2015-06-23 20:57:38 -07:00 committed by Andreas Färber
parent 51d373cf5f
commit 6b625fde5e
2 changed files with 16 additions and 8 deletions
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8
disas.c
View File

@ -257,14 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
#elif defined(TARGET_ALPHA) #elif defined(TARGET_ALPHA)
s.info.mach = bfd_mach_alpha_ev6; s.info.mach = bfd_mach_alpha_ev6;
s.info.print_insn = print_insn_alpha; s.info.print_insn = print_insn_alpha;
#elif defined(TARGET_CRIS)
if (flags != 32) {
s.info.mach = bfd_mach_cris_v0_v10;
s.info.print_insn = print_insn_crisv10;
} else {
s.info.mach = bfd_mach_cris_v32;
s.info.print_insn = print_insn_crisv32;
}
#elif defined(TARGET_S390X) #elif defined(TARGET_S390X)
s.info.mach = bfd_mach_s390_64; s.info.mach = bfd_mach_s390_64;
s.info.print_insn = print_insn_s390; s.info.print_insn = print_insn_s390;

16
target-cris/cpu.c
View File

@ -161,6 +161,20 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level)
} }
#endif #endif
static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
{
CRISCPU *cc = CRIS_CPU(cpu);
CPUCRISState *env = &cc->env;
if (env->pregs[PR_VR] != 32) {
info->mach = bfd_mach_cris_v0_v10;
info->print_insn = print_insn_crisv10;
} else {
info->mach = bfd_mach_cris_v32;
info->print_insn = print_insn_crisv32;
}
}
static void cris_cpu_initfn(Object *obj) static void cris_cpu_initfn(Object *obj)
{ {
CPUState *cs = CPU(obj); CPUState *cs = CPU(obj);
@ -292,6 +306,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 49; cc->gdb_num_core_regs = 49;
cc->gdb_stop_before_watchpoint = true; cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
} }
static const TypeInfo cris_cpu_type_info = { static const TypeInfo cris_cpu_type_info = {