disas: cris: QOMify target specific disas setup
Move the target_disas() cris specifics to the QOM disas_set_info() hook and delete the cris specific code in disas.c. This also now adds support for monitor_disas() to cris. E.g. (qemu) xp 0x40004000 0000000040004000: 0x1e6f25f0 And before this patch: (qemu) xp/i 0x40004000 0x40004000: Asm output not supported on this arch After: (qemu) xp/i 0x40004000 0x40004000: di (qemu) xp/i 0x40004002 0x40004002: move.d 0xb003c004,$r1 Note: second example is 6-byte misaligned instruction! Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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disas.c
8
disas.c
@ -257,14 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
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#elif defined(TARGET_ALPHA)
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#elif defined(TARGET_ALPHA)
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s.info.mach = bfd_mach_alpha_ev6;
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s.info.mach = bfd_mach_alpha_ev6;
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s.info.print_insn = print_insn_alpha;
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s.info.print_insn = print_insn_alpha;
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#elif defined(TARGET_CRIS)
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if (flags != 32) {
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s.info.mach = bfd_mach_cris_v0_v10;
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s.info.print_insn = print_insn_crisv10;
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} else {
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s.info.mach = bfd_mach_cris_v32;
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s.info.print_insn = print_insn_crisv32;
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}
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#elif defined(TARGET_S390X)
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#elif defined(TARGET_S390X)
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s.info.mach = bfd_mach_s390_64;
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s.info.mach = bfd_mach_s390_64;
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s.info.print_insn = print_insn_s390;
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s.info.print_insn = print_insn_s390;
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@ -161,6 +161,20 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level)
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}
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}
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#endif
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#endif
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static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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CRISCPU *cc = CRIS_CPU(cpu);
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CPUCRISState *env = &cc->env;
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if (env->pregs[PR_VR] != 32) {
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info->mach = bfd_mach_cris_v0_v10;
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info->print_insn = print_insn_crisv10;
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} else {
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info->mach = bfd_mach_cris_v32;
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info->print_insn = print_insn_crisv32;
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}
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}
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static void cris_cpu_initfn(Object *obj)
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static void cris_cpu_initfn(Object *obj)
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{
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{
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CPUState *cs = CPU(obj);
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CPUState *cs = CPU(obj);
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@ -292,6 +306,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_num_core_regs = 49;
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cc->gdb_num_core_regs = 49;
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cc->gdb_stop_before_watchpoint = true;
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cc->gdb_stop_before_watchpoint = true;
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cc->disas_set_info = cris_disas_set_info;
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}
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}
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static const TypeInfo cris_cpu_type_info = {
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static const TypeInfo cris_cpu_type_info = {
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