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target/arm: revector to run-time pick target EL

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On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
that that is always EL3, so make room for the value to be computed at
run-time.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rémi Denis-Courmont 2021-01-12 12:45:08 +02:00 committed by Peter Maydell
parent 9861248f63
commit 6b340aeb48
1 changed files with 21 additions and 2 deletions
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23
target/arm/translate.c
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@ -1094,6 +1094,22 @@ static void unallocated_encoding(DisasContext *s)
default_exception_el(s));
}
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
TCGv_i32 tcg_el)
{
TCGv_i32 tcg_excp;
TCGv_i32 tcg_syn;
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_excp = tcg_const_i32(excp);
tcg_syn = tcg_const_i32(syn);
gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
tcg_temp_free_i32(tcg_syn);
tcg_temp_free_i32(tcg_excp);
s->base.is_jmp = DISAS_NORETURN;
}
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@ -2818,8 +2834,11 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
/* If we're in Secure EL1 (which implies that EL3 is AArch64)
* then accesses to Mon registers trap to EL3
*/
exc_target = 3;
goto undef;
TCGv_i32 tcg_el = tcg_const_i32(3);
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
tcg_temp_free_i32(tcg_el);
return false;
}
break;
case ARM_CPU_MODE_HYP: