mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw/misc/mps2-scc: Implement changes for AN547

Browse Source 
Implement the minor changes required to the SCC block for AN547 images:
 * CFG2 and CFG5 exist (like AN524)
 * CFG3 is reserved (like AN524)
 * CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
   in the TODO comment

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-40-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:46:12 +00:00
parent 39901aea06
commit 6ac8081894
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
hw/misc/mps2-scc.c
View File

@ -110,14 +110,14 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
r = s->cfg1; r = s->cfg1;
break; break;
case A_CFG2: case A_CFG2:
if (scc_partno(s) != 0x524) { if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG2 reserved on other boards */ /* CFG2 reserved on other boards */
goto bad_offset; goto bad_offset;
} }
r = s->cfg2; r = s->cfg2;
break; break;
case A_CFG3: case A_CFG3:
if (scc_partno(s) == 0x524) { if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
/* CFG3 reserved on AN524 */ /* CFG3 reserved on AN524 */
goto bad_offset; goto bad_offset;
} }
@ -130,7 +130,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
r = s->cfg4; r = s->cfg4;
break; break;
case A_CFG5: case A_CFG5:
if (scc_partno(s) != 0x524) { if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG5 reserved on other boards */ /* CFG5 reserved on other boards */
goto bad_offset; goto bad_offset;
} }
@ -185,7 +185,10 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
switch (offset) { switch (offset) {
case A_CFG0: case A_CFG0:
/* TODO on some boards bit 0 controls RAM remapping */ /*
* TODO on some boards bit 0 controls RAM remapping;
* on others bit 1 is CPU_WAIT.
*/
s->cfg0 = value; s->cfg0 = value;
break; break;
case A_CFG1: case A_CFG1:
@ -195,7 +198,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
} }
break; break;
case A_CFG2: case A_CFG2:
if (scc_partno(s) != 0x524) { if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG2 reserved on other boards */ /* CFG2 reserved on other boards */
goto bad_offset; goto bad_offset;
} }
@ -203,7 +206,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
s->cfg2 = value; s->cfg2 = value;
break; break;
case A_CFG5: case A_CFG5:
if (scc_partno(s) != 0x524) { if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
/* CFG5 reserved on other boards */ /* CFG5 reserved on other boards */
goto bad_offset; goto bad_offset;
} }