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target/i386: Add support for save/load IA32_PKRS MSR

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PKS introduces MSR IA32_PKRS(0x6e1) to manage the supervisor protection
key rights. Page access and writes can be managed via the MSR update
without TLB flushes when permissions change.

Add the support to save/load IA32_PKRS MSR in guest.

Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <20210205083325.13880-2-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Chenyi Qiang 2021-02-05 16:33:24 +08:00 committed by Paolo Bonzini
parent 735754aaa1
commit 6aa4228bd6
1 changed files with 13 additions and 0 deletions
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13
target/i386/kvm/kvm.c
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@ -113,6 +113,7 @@ static bool has_msr_vmx_vmfunc;
static bool has_msr_ucode_rev;
static bool has_msr_vmx_procbased_ctls2;
static bool has_msr_perf_capabs;
static bool has_msr_pkrs;
static uint32_t has_architectural_pmu_version;
static uint32_t num_architectural_pmu_gp_counters;
@ -2087,6 +2088,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_VMX_PROCBASED_CTLS2:
has_msr_vmx_procbased_ctls2 = true;
break;
case MSR_IA32_PKRS:
has_msr_pkrs = true;
break;
}
}
}
@ -2814,6 +2818,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_smi_count) {
kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
}
if (has_msr_pkrs) {
kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
}
if (has_msr_bndcfgs) {
kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
}
@ -3205,6 +3212,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_feature_control) {
kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
}
if (has_msr_pkrs) {
kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
}
if (has_msr_bndcfgs) {
kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
}
@ -3475,6 +3485,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_UMWAIT_CONTROL:
env->umwait = msrs[i].data;
break;
case MSR_IA32_PKRS:
env->pkrs = msrs[i].data;
break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {