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sam460ex: Fix support for memory larger than 1GB

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Fix the encoding of larger memory modules in the SoC registers which
allows specifying more than 1GB memory for sam460ex. Well, only 2GB
due to SoC and firmware restrictions which was the only missing value
compared to what the real hardware supports. The SoC should support up
to 4GB but when setting that the firmware hangs during memory test.
This may be an overflow bug in the firmware which I did not try to
debug but this may affect real hardware as well.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
BALATON Zoltan 2019-01-03 17:27:24 +01:00 committed by David Gibson
parent 70812bf709
commit 6a9938a379
2 changed files with 16 additions and 12 deletions
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22
hw/ppc/ppc440_uc.c
View File

@ -2,7 +2,7 @@
* QEMU PowerPC 440 embedded processors emulation
*
* Copyright (c) 2012 François Revol
* Copyright (c) 2016-2018 BALATON Zoltan
* Copyright (c) 2016-2019 BALATON Zoltan
*
* This work is licensed under the GNU GPL license version 2 or later.
*
@ -505,10 +505,6 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@ -538,11 +534,17 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
case (1 * GiB):
bcr = 0xe000;
break;
case (2 * GiB):
bcr = 0xc000;
break;
case (4 * GiB):
bcr = 0x8000;
break;
default:
error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
return 0;
}
bcr |= ram_base & 0xFF800000;
bcr |= ram_base >> 2 & 0xffe00000;
bcr |= 1;
return bcr;
@ -550,12 +552,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
static inline hwaddr sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
return (bcr & 0xffe00000) << 2;
}
static target_ulong sdram_size(uint32_t bcr)
static uint64_t sdram_size(uint32_t bcr)
{
target_ulong size;
uint64_t size;
int sh;
sh = 1024 - ((bcr >> 6) & 0x3ff);
@ -575,7 +577,7 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
&sdram->ram_memories[i]);
object_unparent(OBJECT(&sdram->containers[i]));
}
sdram->bcr[i] = bcr & 0xFFDEE001;
sdram->bcr[i] = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
sdram_size(bcr));

6
hw/ppc/sam460ex.c
View File

@ -76,9 +76,11 @@
#define UART_FREQ 11059200
#define SDRAM_NR_BANKS 4
/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
/* The SoC could also handle 4 GiB but firmware does not work with that. */
/* Maybe it overflows a signed 32 bit number somewhere? */
static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0
2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 0
};
struct boot_info {