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target-m68k: Introduce DisasCompare

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Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Richard Henderson 2015-08-14 07:59:21 -07:00 committed by Laurent Vivier
parent 620c6cf665
commit 6a432295d7
1 changed files with 61 additions and 24 deletions
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85
target-m68k/translate.c
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@ -759,8 +759,15 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
return NULL_QREG;
}
/* This generates a conditional branch, clobbering all temporaries. */
static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
typedef struct {
TCGCond tcond;
bool g1;
bool g2;
TCGv v1;
TCGv v2;
} DisasCompare;
static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv tmp, tmp2;
TCGCond tcond;
@ -768,61 +775,92 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
update_cc_op(s);
c->g1 = 1;
c->g2 = 0;
c->v2 = tcg_const_i32(0);
switch (cond) {
case 0: /* T */
tcg_gen_br(l1);
return;
case 1: /* F */
return;
c->v1 = c->v2;
tcond = TCG_COND_NEVER;
break;
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
tmp = tcg_temp_new();
tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
c->v1 = tmp = tcg_temp_new();
c->g1 = 0;
tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
tcond = TCG_COND_NE;
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
tmp = QREG_CC_C;
tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
c->v1 = QREG_CC_C;
tcond = TCG_COND_NE;
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
tmp = QREG_CC_Z;
tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE);
c->v1 = QREG_CC_Z;
tcond = TCG_COND_EQ;
break;
case 8: /* VC (!V) */
case 9: /* VS (V) */
tmp = QREG_CC_V;
tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
c->v1 = QREG_CC_V;
tcond = TCG_COND_LT;
break;
case 10: /* PL (!N) */
case 11: /* MI (N) */
tmp = QREG_CC_N;
tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
c->v1 = QREG_CC_N;
tcond = TCG_COND_LT;
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
tmp = tcg_temp_new();
c->v1 = tmp = tcg_temp_new();
c->g1 = 0;
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
tmp = tcg_temp_new();
tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
c->v1 = tmp = tcg_temp_new();
c->g1 = 0;
tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_neg_i32(tmp, tmp);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
tcg_temp_free(tmp2);
tcond = TCG_COND_LT;
break;
default:
/* Should ever happen. */
abort();
}
tcg_gen_brcondi_i32(tcond, tmp, 0, l1);
if ((cond & 1) == 0) {
tcond = tcg_invert_cond(tcond);
}
c->tcond = tcond;
}
static void free_cond(DisasCompare *c)
{
if (!c->g1) {
tcg_temp_free(c->v1);
}
if (!c->g2) {
tcg_temp_free(c->v2);
}
}
static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
{
DisasCompare c;
gen_cc_cond(&c, s, cond);
update_cc_op(s);
tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
free_cond(&c);
}
DISAS_INSN(scc)
@ -1678,7 +1716,6 @@ DISAS_INSN(branch)
/* bsr */
gen_push(s, tcg_const_i32(s->pc));
}
update_cc_op(s);
if (op > 1) {
/* Bcc */
l1 = gen_new_label();