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target/openrisc: Enable MTTCG

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This patch enables multithread TCG for OpenRISC.  Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2022-06-15 08:43:56 +09:00
parent bbe6855ef8
commit 6a0fc96ad2
3 changed files with 9 additions and 1 deletions
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1
configs/targets/or1k-softmmu.mak
View File

@ -1,3 +1,4 @@
TARGET_ARCH=openrisc
TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y

2
target/openrisc/cpu.h
View File

@ -25,6 +25,8 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TCG_GUEST_DEFAULT_MO (0)
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)

7
target/openrisc/sys_helper.c
View File

@ -145,6 +145,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(10, 0): /* TTMR */
{
qemu_mutex_lock_iothread();
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
switch (rb & TTMR_M) {
case TIMER_NONE:
@ -168,14 +169,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
cpu_openrisc_timer_update(cpu);
qemu_mutex_unlock_iothread();
}
break;
case TO_SPR(10, 1): /* TTCR */
qemu_mutex_lock_iothread();
cpu_openrisc_count_set(cpu, rb);
cpu_openrisc_timer_update(cpu);
qemu_mutex_unlock_iothread();
break;
#endif
@ -303,7 +306,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return env->ttmr;
case TO_SPR(10, 1): /* TTCR */
qemu_mutex_lock_iothread();
cpu_openrisc_count_update(cpu);
qemu_mutex_unlock_iothread();
return cpu_openrisc_count_get(cpu);
#endif