mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg/tci: Split out tci_qemu_ld, tci_qemu_st

Browse Source 
We can share this code between 32-bit and 64-bit loads and stores.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-27 12:21:59 -07:00
parent 08096b1a64
commit 69acc02a8b
1 changed files with 71 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

183
tcg/tci.c
View File

@ -317,6 +317,73 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
#define qemu_st_beq(X) \
cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
TCGMemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
switch (mop) {
case MO_UB:
return qemu_ld_ub;
case MO_SB:
return (int8_t)qemu_ld_ub;
case MO_LEUW:
return qemu_ld_leuw;
case MO_LESW:
return (int16_t)qemu_ld_leuw;
case MO_LEUL:
return qemu_ld_leul;
case MO_LESL:
return (int32_t)qemu_ld_leul;
case MO_LEQ:
return qemu_ld_leq;
case MO_BEUW:
return qemu_ld_beuw;
case MO_BESW:
return (int16_t)qemu_ld_beuw;
case MO_BEUL:
return qemu_ld_beul;
case MO_BESL:
return (int32_t)qemu_ld_beul;
case MO_BEQ:
return qemu_ld_beq;
default:
g_assert_not_reached();
}
}
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
TCGMemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
switch (mop) {
case MO_UB:
qemu_st_b(val);
break;
case MO_LEUW:
qemu_st_lew(val);
break;
case MO_LEUL:
qemu_st_lel(val);
break;
case MO_LEQ:
qemu_st_leq(val);
break;
case MO_BEUW:
qemu_st_bew(val);
break;
case MO_BEUL:
qemu_st_bel(val);
break;
case MO_BEQ:
qemu_st_beq(val);
break;
default:
g_assert_not_reached();
}
}
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
@ -909,34 +976,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp32 = qemu_ld_ub;
break;
case MO_SB:
tmp32 = (int8_t)qemu_ld_ub;
break;
case MO_LEUW:
tmp32 = qemu_ld_leuw;
break;
case MO_LESW:
tmp32 = (int16_t)qemu_ld_leuw;
break;
case MO_LEUL:
tmp32 = qemu_ld_leul;
break;
case MO_BEUW:
tmp32 = qemu_ld_beuw;
break;
case MO_BESW:
tmp32 = (int16_t)qemu_ld_beuw;
break;
case MO_BEUL:
tmp32 = qemu_ld_beul;
break;
default:
g_assert_not_reached();
}
tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
regs[r0] = tmp32;
break;
@ -952,46 +992,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r3], regs[r2]);
oi = regs[r4];
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp64 = qemu_ld_ub;
break;
case MO_SB:
tmp64 = (int8_t)qemu_ld_ub;
break;
case MO_LEUW:
tmp64 = qemu_ld_leuw;
break;
case MO_LESW:
tmp64 = (int16_t)qemu_ld_leuw;
break;
case MO_LEUL:
tmp64 = qemu_ld_leul;
break;
case MO_LESL:
tmp64 = (int32_t)qemu_ld_leul;
break;
case MO_LEQ:
tmp64 = qemu_ld_leq;
break;
case MO_BEUW:
tmp64 = qemu_ld_beuw;
break;
case MO_BESW:
tmp64 = (int16_t)qemu_ld_beuw;
break;
case MO_BEUL:
tmp64 = qemu_ld_beul;
break;
case MO_BESL:
tmp64 = (int32_t)qemu_ld_beul;
break;
case MO_BEQ:
tmp64 = qemu_ld_beq;
break;
default:
g_assert_not_reached();
}
tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, r1, r0, tmp64);
} else {
@ -1008,25 +1009,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp32);
break;
case MO_LEUW:
qemu_st_lew(tmp32);
break;
case MO_LEUL:
qemu_st_lel(tmp32);
break;
case MO_BEUW:
qemu_st_bew(tmp32);
break;
case MO_BEUL:
qemu_st_bel(tmp32);
break;
default:
g_assert_not_reached();
}
tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
break;
case INDEX_op_qemu_st_i64:
@ -1045,31 +1028,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp64);
break;
case MO_LEUW:
qemu_st_lew(tmp64);
break;
case MO_LEUL:
qemu_st_lel(tmp64);
break;
case MO_LEQ:
qemu_st_leq(tmp64);
break;
case MO_BEUW:
qemu_st_bew(tmp64);
break;
case MO_BEUL:
qemu_st_bel(tmp64);
break;
case MO_BEQ:
qemu_st_beq(tmp64);
break;
default:
g_assert_not_reached();
}
tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
break;
case INDEX_op_mb: