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target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess

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vmvr_v isn't handling the case where the host might be big endian and
the bytes to be copied aren't sequential.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240314175704.478276-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 768e7b329c0be22035da077fe76221dd0a47103b)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Daniel Henrique Barboza 2024-03-14 14:56:57 -03:00 committed by Michael Tokarev
parent 9f0db88ca9
commit 693ceca987
1 changed files with 9 additions and 1 deletions
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10
target/riscv/vector_helper.c
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@ -5064,9 +5064,17 @@ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
uint32_t startb = env->vstart * sewb;
uint32_t i = startb;
if (HOST_BIG_ENDIAN && i % 8 != 0) {
uint32_t j = ROUND_UP(i, 8);
memcpy((uint8_t *)vd + H1(j - 1),
(uint8_t *)vs2 + H1(j - 1),
j - i);
i = j;
}
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
maxsz - startb);
maxsz - i);
env->vstart = 0;
}