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target/riscv: Use gen_shift_imm_fn for slli_uw

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Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-21-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:25 -07:00 committed by Alistair Francis
parent cce762a75e
commit 6922eee6ac
1 changed files with 6 additions and 13 deletions
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19
target/riscv/insn_trans/trans_rvb.c.inc
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@ -635,21 +635,14 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
return gen_arith(ctx, a, EXT_NONE, gen_add_uw); return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
} }
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
{
tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
}
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB); REQUIRE_EXT(ctx, RVB);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
TCGv source1 = tcg_temp_new();
gen_get_gpr(ctx, source1, a->rs1);
if (a->shamt < 32) {
tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
} else {
tcg_gen_shli_tl(source1, source1, a->shamt);
}
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(source1);
return true;
} }