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ppc4xx_sdram: Get rid of the init RAM hack

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The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_init hack.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <d6c44c870befa1a075e21f1a59926dcdaff63f6b.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-09-24 14:27:52 +02:00 committed by Daniel Henrique Barboza
parent 8626982301
commit 68b9a2e38d
6 changed files with 15 additions and 14 deletions
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1
hw/ppc/ppc405.h
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@ -169,7 +169,6 @@ struct Ppc405SoCState {
/* Public */ /* Public */
MemoryRegion ram_banks[2]; MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2]; hwaddr ram_bases[2], ram_sizes[2];
bool do_dram_init;
MemoryRegion *dram_mr; MemoryRegion *dram_mr;
hwaddr ram_size; hwaddr ram_size;

3
hw/ppc/ppc405_boards.c
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@ -288,8 +288,6 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal); machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram", object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort); OBJECT(machine->ram), &error_abort);
object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
kernel_filename != NULL, &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
&error_abort); &error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal); qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
@ -349,6 +347,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */ /* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) { } else if (kernel_filename && !machine->firmware) {
ppc4xx_sdram_enable(&ppc405->soc.cpu.env);
boot_from_kernel(machine, &ppc405->soc.cpu); boot_from_kernel(machine, &ppc405->soc.cpu);
} }
} }

4
hw/ppc/ppc405_uc.c
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@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->ram_bases[0], s->ram_sizes[0]); s->ram_bases[0], s->ram_sizes[0]);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
s->ram_banks, s->ram_bases, s->ram_sizes, s->ram_banks, s->ram_bases, s->ram_sizes);
s->do_dram_init);
/* External bus controller */ /* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = { static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *), MemoryRegion *),
DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

4
hw/ppc/ppc440_bamboo.c
View File

@ -211,7 +211,9 @@ static void bamboo_init(MachineState *machine)
ppc4xx_sdram_init(env, ppc4xx_sdram_init(env,
qdev_get_gpio_in(uicdev, 14), qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_memories, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, 1); ram_bases, ram_sizes);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);
/* PCI */ /* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,

12
hw/ppc/ppc4xx_devs.c
View File

@ -350,8 +350,7 @@ static void sdram_reset(void *opaque)
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories, MemoryRegion *ram_memories,
hwaddr *ram_bases, hwaddr *ram_bases,
hwaddr *ram_sizes, hwaddr *ram_sizes)
int do_init)
{ {
ppc4xx_sdram_t *sdram; ppc4xx_sdram_t *sdram;
int i; int i;
@ -369,9 +368,12 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram); sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA, ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram); sdram, &dcr_read_sdram, &dcr_write_sdram);
if (do_init) { }
sdram_map_bcr(sdram);
} void ppc4xx_sdram_enable(CPUPPCState *env)
{
ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20);
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000);
} }
/* /*

5
include/hw/ppc/ppc4xx.h
View File

@ -37,6 +37,8 @@ typedef struct {
uint32_t bcr; uint32_t bcr;
} Ppc4xxSdramBank; } Ppc4xxSdramBank;
void ppc4xx_sdram_enable(CPUPPCState *env);
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[], MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[], hwaddr ram_bases[], hwaddr ram_sizes[],
@ -45,8 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[], MemoryRegion ram_memories[],
hwaddr *ram_bases, hwaddr *ram_bases,
hwaddr *ram_sizes, hwaddr *ram_sizes);
int do_init);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"