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BSR/BSF undefined behaviour fix

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@809 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2004-05-16 15:56:04 +00:00
parent 5b1214a48e
commit 686f3f266b
2 changed files with 6 additions and 5 deletions
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4
target-i386/ops_template.h
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@ -513,7 +513,7 @@ void OPPROTO glue(glue(op_bsf, SUFFIX), _T0_cc)(void)
count++;
res >>= 1;
}
T0 = count;
T1 = count;
CC_DST = 1; /* ZF = 0 */
} else {
CC_DST = 0; /* ZF = 1 */
@ -531,7 +531,7 @@ void OPPROTO glue(glue(op_bsr, SUFFIX), _T0_cc)(void)
count--;
res <<= 1;
}
T0 = count;
T1 = count;
CC_DST = 1; /* ZF = 0 */
} else {
CC_DST = 0; /* ZF = 1 */

7
target-i386/translate.c
View File

@ -3708,10 +3708,11 @@ static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
modrm = ldub_code(s->pc++);
reg = (modrm >> 3) & 7;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
/* NOTE: in order to handle the 0 case, we must load the
result. It could be optimized with a generated jump */
gen_op_mov_TN_reg[ot][1][reg]();
gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
/* NOTE: we always write back the result. Intel doc says it is
undefined if T0 == 0 */
gen_op_mov_reg_T0[ot][reg]();
gen_op_mov_reg_T1[ot][reg]();
s->cc_op = CC_OP_LOGICB + ot;
break;
/************************/