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tcg/sparc: Improve code gen for shifted 32-bit constants

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We had code for checking for 13 and 21-bit shifted constants,
but we can do better and allow 32-bit shifted constants.
This is still 2 insns shorter than the full 64-bit sequence.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-08-05 04:09:15 +03:00
parent 92840d06fa
commit 684db2a0b0
1 changed files with 6 additions and 6 deletions
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12
tcg/sparc/tcg-target.c.inc
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@ -462,17 +462,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
return;
}
/* A 21-bit constant, shifted. */
/* A 32-bit constant, shifted. */
lsb = ctz64(arg);
test = (tcg_target_long)arg >> lsb;
if (check_fit_tl(test, 13)) {
tcg_out_movi_imm13(s, ret, test);
tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
return;
} else if (lsb > 10 && test == extract64(test, 0, 21)) {
if (lsb > 10 && test == extract64(test, 0, 21)) {
tcg_out_sethi(s, ret, test << 10);
tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
return;
} else if (test == (uint32_t)test || test == (int32_t)test) {
tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch);
tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
return;
}
/* A 64-bit constant decomposed into 2 32-bit pieces. */