target/arm: Implement SVE load and broadcast element
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -274,6 +274,11 @@ DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_movz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_asr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_asr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_asr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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@ -28,6 +28,7 @@
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%imm8_16_10 16:5 10:3
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%imm9_16_10 16:s6 10:3
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%size_23 23:2
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%dtype_23_13 23:2 13:2
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# A combination of tsz:imm3 -- extract esize.
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%tszimm_esz 22:2 5:5 !function=tszimm_esz
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@ -751,6 +752,10 @@ LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
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# SVE load vector register
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LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
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# SVE load and broadcast element
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LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
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&rpri_load dtype=%dtype_23_13 nreg=0
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### SVE Memory Contiguous Load Group
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# SVE contiguous load (scalar plus scalar)
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@ -995,6 +995,47 @@ void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc)
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}
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}
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/* Copy Zn into Zd, and store zero into inactive elements. */
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void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = n[i] & expand_pred_b(pg[H1(i)]);
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}
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}
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void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = n[i] & expand_pred_h(pg[H1(i)]);
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}
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}
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void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = n[i] & expand_pred_s(pg[H1(i)]);
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}
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}
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void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = n[1] & -(uint64_t)(pg[H1(i)] & 1);
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}
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}
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/* Three-operand expander, immediate operand, controlled by a predicate.
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*/
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#define DO_ZPZI(NAME, TYPE, H, OP) \
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@ -606,6 +606,20 @@ static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz)
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return true;
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}
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/* Copy Zn into Zd, storing zeros into inactive elements. */
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static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz)
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{
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static gen_helper_gvec_3 * const fns[4] = {
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gen_helper_sve_movz_b, gen_helper_sve_movz_h,
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gen_helper_sve_movz_s, gen_helper_sve_movz_d,
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};
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unsigned vsz = vec_full_reg_size(s);
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tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn),
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pred_full_reg_offset(s, pg),
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vsz, vsz, 0, fns[esz]);
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}
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static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
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gen_helper_gvec_3 *fn)
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{
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@ -3999,6 +4013,54 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
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return true;
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}
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/* Load and broadcast element. */
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static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
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{
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if (!sve_access_check(s)) {
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return true;
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}
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unsigned vsz = vec_full_reg_size(s);
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unsigned psz = pred_full_reg_size(s);
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unsigned esz = dtype_esz[a->dtype];
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TCGLabel *over = gen_new_label();
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TCGv_i64 temp;
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/* If the guarding predicate has no bits set, no load occurs. */
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if (psz <= 8) {
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/* Reduce the pred_esz_masks value simply to reduce the
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* size of the code generated here.
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*/
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uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8);
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temp = tcg_temp_new_i64();
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tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg));
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tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask);
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tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over);
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tcg_temp_free_i64(temp);
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} else {
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TCGv_i32 t32 = tcg_temp_new_i32();
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find_last_active(s, t32, esz, a->pg);
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tcg_gen_brcondi_i32(TCG_COND_LT, t32, 0, over);
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tcg_temp_free_i32(t32);
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}
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/* Load the data. */
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temp = tcg_temp_new_i64();
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tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
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tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
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s->be_data | dtype_mop[a->dtype]);
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/* Broadcast to *all* elements. */
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tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),
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vsz, vsz, temp);
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tcg_temp_free_i64(temp);
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/* Zero the inactive elements. */
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gen_set_label(over);
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do_movz_zpz(s, a->rd, a->rd, a->pg, esz);
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return true;
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}
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static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
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int msz, int esz, int nreg)
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{
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