mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/sparc: Implement UMULXHI

Browse Source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 18:22:42 -07:00
parent 7d5ebd8ffe
commit 680af1b4a5
2 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/sparc/insns.decode
View File

@ -389,6 +389,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
ADDXC 10 ..... 110110 ..... 0 0001 0001 ..... @r_r_r
ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r
UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r
LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r

8
target/sparc/translate.c
View File

@ -581,6 +581,12 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
gen_op_multiply(dst, src1, src2, 1);
}
static void gen_op_umulxhi(TCGv dst, TCGv src1, TCGv src2)
{
TCGv discard = tcg_temp_new();
tcg_gen_mulu2_tl(discard, dst, src1, src2);
}
static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
{
#ifdef TARGET_SPARC64
@ -3919,6 +3925,8 @@ TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32)
TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc)
TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc)
TRANS(UMULXHI, VIS3, do_rrr, a, gen_op_umulxhi)
static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2)
{
#ifdef TARGET_SPARC64