hw/nvram: Introduce Xilinx ZynqMP eFuse device
This implements the Xilinx ZynqMP eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx ZynqMP product family. Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tong Ho
Peter Maydell
parent
9e4aa1fafe
commit
67fa02f89f
@ -26,3 +26,7 @@ config XLNX_EFUSE
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config XLNX_EFUSE_VERSAL
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bool
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select XLNX_EFUSE
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config XLNX_EFUSE_ZYNQMP
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bool
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select XLNX_EFUSE
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@ -14,5 +14,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
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'xlnx-versal-efuse-cache.c',
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'xlnx-versal-efuse-ctrl.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
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'xlnx-zynqmp-efuse.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
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855
hw/nvram/xlnx-zynqmp-efuse.c
Normal file
855
hw/nvram/xlnx-zynqmp-efuse.c
Normal file
@ -0,0 +1,855 @@
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/*
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* QEMU model of the ZynqMP eFuse
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*
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* Copyright (c) 2015 Xilinx Inc.
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*
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* Written by Edgar E. Iglesias <edgari@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/nvram/xlnx-zynqmp-efuse.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#ifndef ZYNQMP_EFUSE_ERR_DEBUG
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#define ZYNQMP_EFUSE_ERR_DEBUG 0
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#endif
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REG32(WR_LOCK, 0x0)
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FIELD(WR_LOCK, LOCK, 0, 16)
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REG32(CFG, 0x4)
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FIELD(CFG, SLVERR_ENABLE, 5, 1)
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FIELD(CFG, MARGIN_RD, 2, 2)
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FIELD(CFG, PGM_EN, 1, 1)
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FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
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REG32(STATUS, 0x8)
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FIELD(STATUS, AES_CRC_PASS, 7, 1)
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FIELD(STATUS, AES_CRC_DONE, 6, 1)
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FIELD(STATUS, CACHE_DONE, 5, 1)
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FIELD(STATUS, CACHE_LOAD, 4, 1)
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FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
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FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
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FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
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REG32(EFUSE_PGM_ADDR, 0xc)
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FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
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FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
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FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
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REG32(EFUSE_RD_ADDR, 0x10)
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FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
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FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
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REG32(EFUSE_RD_DATA, 0x14)
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REG32(TPGM, 0x18)
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FIELD(TPGM, VALUE, 0, 16)
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REG32(TRD, 0x1c)
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FIELD(TRD, VALUE, 0, 8)
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REG32(TSU_H_PS, 0x20)
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FIELD(TSU_H_PS, VALUE, 0, 8)
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REG32(TSU_H_PS_CS, 0x24)
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FIELD(TSU_H_PS_CS, VALUE, 0, 8)
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REG32(TSU_H_CS, 0x2c)
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FIELD(TSU_H_CS, VALUE, 0, 4)
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REG32(EFUSE_ISR, 0x30)
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FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
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FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
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FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
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FIELD(EFUSE_ISR, RD_DONE, 2, 1)
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FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
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FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
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REG32(EFUSE_IMR, 0x34)
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FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
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FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
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FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
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FIELD(EFUSE_IMR, RD_DONE, 2, 1)
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FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
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FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
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REG32(EFUSE_IER, 0x38)
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FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
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FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
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FIELD(EFUSE_IER, RD_ERROR, 3, 1)
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FIELD(EFUSE_IER, RD_DONE, 2, 1)
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FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
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FIELD(EFUSE_IER, PGM_DONE, 0, 1)
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REG32(EFUSE_IDR, 0x3c)
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FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
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FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
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FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
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FIELD(EFUSE_IDR, RD_DONE, 2, 1)
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FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
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FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
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REG32(EFUSE_CACHE_LOAD, 0x40)
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FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
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REG32(EFUSE_PGM_LOCK, 0x44)
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FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
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REG32(EFUSE_AES_CRC, 0x48)
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REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
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FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
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REG32(DNA_0, 0x100c)
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REG32(DNA_1, 0x1010)
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REG32(DNA_2, 0x1014)
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REG32(IPDISABLE, 0x1018)
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FIELD(IPDISABLE, VCU_DIS, 8, 1)
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FIELD(IPDISABLE, GPU_DIS, 5, 1)
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FIELD(IPDISABLE, APU3_DIS, 3, 1)
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FIELD(IPDISABLE, APU2_DIS, 2, 1)
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FIELD(IPDISABLE, APU1_DIS, 1, 1)
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FIELD(IPDISABLE, APU0_DIS, 0, 1)
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REG32(SYSOSC_CTRL, 0x101c)
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FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
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REG32(USER_0, 0x1020)
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REG32(USER_1, 0x1024)
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REG32(USER_2, 0x1028)
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REG32(USER_3, 0x102c)
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REG32(USER_4, 0x1030)
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REG32(USER_5, 0x1034)
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REG32(USER_6, 0x1038)
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REG32(USER_7, 0x103c)
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REG32(MISC_USER_CTRL, 0x1040)
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FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
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FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
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FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
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FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
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REG32(ROM_RSVD, 0x1044)
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FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
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REG32(PUF_CHASH, 0x1050)
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REG32(PUF_MISC, 0x1054)
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FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
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FIELD(PUF_MISC, SYN_WRLK, 30, 1)
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FIELD(PUF_MISC, SYN_INVLD, 29, 1)
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FIELD(PUF_MISC, TEST2_DIS, 28, 1)
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FIELD(PUF_MISC, UNUSED27, 27, 1)
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FIELD(PUF_MISC, UNUSED26, 26, 1)
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FIELD(PUF_MISC, UNUSED25, 25, 1)
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FIELD(PUF_MISC, UNUSED24, 24, 1)
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FIELD(PUF_MISC, AUX, 0, 24)
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REG32(SEC_CTRL, 0x1058)
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FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
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FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
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FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
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FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
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FIELD(SEC_CTRL, RSA_EN, 11, 15)
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FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
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FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
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FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
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FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
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FIELD(SEC_CTRL, DFT_DIS, 6, 1)
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FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
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FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
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FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
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FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
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FIELD(SEC_CTRL, AES_WRLK, 1, 1)
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FIELD(SEC_CTRL, AES_RDLK, 0, 1)
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REG32(SPK_ID, 0x105c)
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REG32(PPK0_0, 0x10a0)
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REG32(PPK0_1, 0x10a4)
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REG32(PPK0_2, 0x10a8)
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REG32(PPK0_3, 0x10ac)
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REG32(PPK0_4, 0x10b0)
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REG32(PPK0_5, 0x10b4)
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REG32(PPK0_6, 0x10b8)
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REG32(PPK0_7, 0x10bc)
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REG32(PPK0_8, 0x10c0)
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REG32(PPK0_9, 0x10c4)
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REG32(PPK0_10, 0x10c8)
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REG32(PPK0_11, 0x10cc)
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REG32(PPK1_0, 0x10d0)
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REG32(PPK1_1, 0x10d4)
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REG32(PPK1_2, 0x10d8)
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REG32(PPK1_3, 0x10dc)
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REG32(PPK1_4, 0x10e0)
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REG32(PPK1_5, 0x10e4)
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REG32(PPK1_6, 0x10e8)
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REG32(PPK1_7, 0x10ec)
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REG32(PPK1_8, 0x10f0)
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REG32(PPK1_9, 0x10f4)
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REG32(PPK1_10, 0x10f8)
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REG32(PPK1_11, 0x10fc)
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#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
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#define R_MAX (R_PPK1_11 + 1)
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/* #define EFUSE_XOSC 26 */
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/*
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* eFUSE layout references:
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* ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
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*/
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#define EFUSE_AES_RDLK BIT_POS(22, 0)
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#define EFUSE_AES_WRLK BIT_POS(22, 1)
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#define EFUSE_ENC_ONLY BIT_POS(22, 2)
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#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
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#define EFUSE_ERROR_DIS BIT_POS(22, 4)
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#define EFUSE_JTAG_DIS BIT_POS(22, 5)
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#define EFUSE_DFT_DIS BIT_POS(22, 6)
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#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
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#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
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#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
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#define EFUSE_SEC_LOCK BIT_POS(22, 10)
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#define EFUSE_RSA_EN BIT_POS(22, 11)
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#define EFUSE_RSA_EN14 BIT_POS(22, 25)
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#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
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#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
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#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
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#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
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#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
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#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
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/* Areas. */
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#define EFUSE_TRIM_START BIT_POS(1, 0)
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#define EFUSE_TRIM_END BIT_POS(1, 30)
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#define EFUSE_DNA_START BIT_POS(3, 0)
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#define EFUSE_DNA_END BIT_POS(5, 31)
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#define EFUSE_AES_START BIT_POS(24, 0)
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#define EFUSE_AES_END BIT_POS(31, 31)
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#define EFUSE_ROM_START BIT_POS(17, 0)
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#define EFUSE_ROM_END BIT_POS(17, 31)
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#define EFUSE_IPDIS_START BIT_POS(6, 0)
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#define EFUSE_IPDIS_END BIT_POS(6, 31)
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#define EFUSE_USER_START BIT_POS(8, 0)
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#define EFUSE_USER_END BIT_POS(15, 31)
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#define EFUSE_BISR_START BIT_POS(32, 0)
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#define EFUSE_BISR_END BIT_POS(39, 31)
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#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
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#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
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#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
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#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
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#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
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#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
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#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
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#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
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#define EFUSE_SPK_START BIT_POS(23, 0)
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#define EFUSE_SPK_END BIT_POS(23, 31)
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#define EFUSE_PPK0_START BIT_POS(40, 0)
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#define EFUSE_PPK0_END BIT_POS(51, 31)
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#define EFUSE_PPK1_START BIT_POS(52, 0)
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#define EFUSE_PPK1_END BIT_POS(63, 31)
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#define EFUSE_CACHE_FLD(s, reg, field) \
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ARRAY_FIELD_DP32((s)->regs, reg, field, \
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(xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
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>> (EFUSE_ ## field % 32)))
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#define EFUSE_CACHE_BIT(s, reg, field) \
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ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
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EFUSE_ ## field))
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#define FBIT_UNKNOWN (~0)
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QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
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static void update_tbit_status(XlnxZynqMPEFuse *s)
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{
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unsigned int check = xlnx_efuse_tbits_check(s->efuse);
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uint32_t val = s->regs[R_STATUS];
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val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
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val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
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val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
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s->regs[R_STATUS] = val;
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}
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/* Update the u32 array from efuse bits. Slow but simple approach. */
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static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
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unsigned int f_start, unsigned int f_end,
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unsigned int f_written)
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{
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uint32_t *u32 = &s->regs[r_start];
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unsigned int fbit, wbits = 0, u32_off = 0;
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/* Avoid working on bits that are not relevant. */
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if (f_written != FBIT_UNKNOWN
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&& (f_written < f_start || f_written > f_end)) {
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return;
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}
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for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
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if (wbits == 32) {
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/* Update the key offset. */
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u32_off += 1;
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wbits = 0;
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}
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u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
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}
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}
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/*
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* Keep the syncs in bit order so we can bail out for the
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* slower ones.
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*/
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static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
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{
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EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
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EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
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EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
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EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
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EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
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EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
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EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
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EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
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EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
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EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
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||||
EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
|
||||
EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
|
||||
EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
|
||||
|
||||
EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
|
||||
EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
|
||||
EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
|
||||
|
||||
/* Update the tbits. */
|
||||
update_tbit_status(s);
|
||||
|
||||
/* Sync the various areas. */
|
||||
s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
|
||||
EFUSE_USER_CTRL_START)
|
||||
& EFUSE_USER_CTRL_MASK;
|
||||
s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
|
||||
s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
|
||||
|
||||
cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
|
||||
|
||||
if (bit < EFUSE_AES_START) {
|
||||
return;
|
||||
}
|
||||
|
||||
cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
|
||||
cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
|
||||
cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
|
||||
cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
|
||||
cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
|
||||
cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
|
||||
{
|
||||
bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
|
||||
qemu_set_irq(s->irq, pending);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
}
|
||||
|
||||
static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
uint32_t val = val64;
|
||||
|
||||
s->regs[R_EFUSE_IMR] |= val;
|
||||
zynqmp_efuse_update_irq(s);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
uint32_t val = val64;
|
||||
|
||||
s->regs[R_EFUSE_IMR] &= ~val;
|
||||
zynqmp_efuse_update_irq(s);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
unsigned bit = val64;
|
||||
unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
|
||||
bool puf_prot = false;
|
||||
const char *errmsg = NULL;
|
||||
|
||||
/* Allow only valid array, and adjust for skipped array 1 */
|
||||
switch (page) {
|
||||
case 0:
|
||||
break;
|
||||
case 2 ... 3:
|
||||
bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
|
||||
puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
|
||||
break;
|
||||
default:
|
||||
errmsg = "Invalid address";
|
||||
goto pgm_done;
|
||||
}
|
||||
|
||||
if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
|
||||
errmsg = "Array write-locked";
|
||||
goto pgm_done;
|
||||
}
|
||||
|
||||
if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
|
||||
errmsg = "Array pgm-disabled";
|
||||
goto pgm_done;
|
||||
}
|
||||
|
||||
if (puf_prot) {
|
||||
errmsg = "PUF_HD-store write-locked";
|
||||
goto pgm_done;
|
||||
}
|
||||
|
||||
if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
|
||||
&& bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
|
||||
errmsg = "AES key-store Write-locked";
|
||||
goto pgm_done;
|
||||
}
|
||||
|
||||
if (!xlnx_efuse_set_bit(s->efuse, bit)) {
|
||||
errmsg = "Write failed";
|
||||
}
|
||||
|
||||
pgm_done:
|
||||
if (!errmsg) {
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
|
||||
} else {
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s - eFuse write error: %s; addr=0x%x\n",
|
||||
object_get_canonical_path(OBJECT(s)),
|
||||
errmsg, (unsigned)val64);
|
||||
}
|
||||
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
|
||||
/*
|
||||
* Grant reads only to allowed bits; reference sources:
|
||||
* 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
|
||||
* 2/ UG1085, v2.0, table 12-13
|
||||
* (note: enumerates the masks as <first, last> per described in
|
||||
* references to avoid mental translation).
|
||||
*/
|
||||
#define COL_MASK(L_, H_) \
|
||||
((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
|
||||
|
||||
static const uint32_t ary0_col_mask[] = {
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
|
||||
[0] = COL_MASK(28, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
|
||||
[8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
|
||||
[10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
|
||||
[12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
|
||||
[14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
|
||||
[16] = COL_MASK(0, 7) | COL_MASK(10, 16),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
|
||||
[17] = COL_MASK(0, 2),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
|
||||
[20] = COL_MASK(0, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
|
||||
[21] = COL_MASK(0, 23) | COL_MASK(29, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
|
||||
[22] = COL_MASK(0, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
|
||||
[23] = COL_MASK(0, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
|
||||
[40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
|
||||
[42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
|
||||
[44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
|
||||
[46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
|
||||
[48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
|
||||
[50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
|
||||
|
||||
/* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
|
||||
[52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
|
||||
[54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
|
||||
[56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
|
||||
[58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
|
||||
[60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
|
||||
[62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
|
||||
};
|
||||
|
||||
uint32_t col_mask = COL_MASK(0, 31);
|
||||
#undef COL_MASK
|
||||
|
||||
uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
|
||||
uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
|
||||
uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
|
||||
|
||||
switch (efuse_ary) {
|
||||
case 0: /* Various */
|
||||
if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
|
||||
goto denied;
|
||||
}
|
||||
|
||||
col_mask = ary0_col_mask[efuse_row];
|
||||
if (!col_mask) {
|
||||
goto denied;
|
||||
}
|
||||
break;
|
||||
case 2: /* PUF helper data, adjust for skipped array 1 */
|
||||
case 3:
|
||||
val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
|
||||
break;
|
||||
default:
|
||||
goto denied;
|
||||
}
|
||||
|
||||
s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
|
||||
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
return;
|
||||
|
||||
denied:
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Denied efuse read from array %u, row %u\n",
|
||||
object_get_canonical_path(OBJECT(s)),
|
||||
efuse_ary, efuse_row);
|
||||
|
||||
s->regs[R_EFUSE_RD_DATA] = 0;
|
||||
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
|
||||
ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
bool ok;
|
||||
|
||||
ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
|
||||
|
||||
ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
|
||||
ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
|
||||
|
||||
s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
|
||||
}
|
||||
|
||||
static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
|
||||
uint64_t valu64)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
|
||||
|
||||
if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
|
||||
zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
|
||||
ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
|
||||
{
|
||||
return val == 0xDF0D ? 0 : 1;
|
||||
}
|
||||
|
||||
static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
|
||||
{ .name = "WR_LOCK", .addr = A_WR_LOCK,
|
||||
.reset = 0x1,
|
||||
.pre_write = zynqmp_efuse_wr_lock_prew,
|
||||
},{ .name = "CFG", .addr = A_CFG,
|
||||
},{ .name = "STATUS", .addr = A_STATUS,
|
||||
.rsvd = 0x8,
|
||||
.ro = 0xff,
|
||||
},{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
|
||||
.post_write = zynqmp_efuse_pgm_addr_postw
|
||||
},{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
|
||||
.rsvd = 0x1f,
|
||||
.post_write = zynqmp_efuse_rd_addr_postw,
|
||||
},{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "TPGM", .addr = A_TPGM,
|
||||
},{ .name = "TRD", .addr = A_TRD,
|
||||
.reset = 0x1b,
|
||||
},{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
|
||||
.reset = 0xff,
|
||||
},{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
|
||||
.reset = 0xb,
|
||||
},{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
|
||||
.reset = 0x7,
|
||||
},{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
|
||||
.rsvd = 0x7fffffe0,
|
||||
.w1c = 0x8000001f,
|
||||
.post_write = zynqmp_efuse_isr_postw,
|
||||
},{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
|
||||
.reset = 0x8000001f,
|
||||
.rsvd = 0x7fffffe0,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
|
||||
.rsvd = 0x7fffffe0,
|
||||
.pre_write = zynqmp_efuse_ier_prew,
|
||||
},{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
|
||||
.rsvd = 0x7fffffe0,
|
||||
.pre_write = zynqmp_efuse_idr_prew,
|
||||
},{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
|
||||
.pre_write = zynqmp_efuse_cache_load_prew,
|
||||
},{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
|
||||
},{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
|
||||
.post_write = zynqmp_efuse_aes_crc_postw,
|
||||
},{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
|
||||
.reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
|
||||
},{ .name = "DNA_0", .addr = A_DNA_0,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "DNA_1", .addr = A_DNA_1,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "DNA_2", .addr = A_DNA_2,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "IPDISABLE", .addr = A_IPDISABLE,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_0", .addr = A_USER_0,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_1", .addr = A_USER_1,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_2", .addr = A_USER_2,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_3", .addr = A_USER_3,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_4", .addr = A_USER_4,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_5", .addr = A_USER_5,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_6", .addr = A_USER_6,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "USER_7", .addr = A_USER_7,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PUF_MISC", .addr = A_PUF_MISC,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "SPK_ID", .addr = A_SPK_ID,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_0", .addr = A_PPK0_0,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_1", .addr = A_PPK0_1,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_2", .addr = A_PPK0_2,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_3", .addr = A_PPK0_3,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_4", .addr = A_PPK0_4,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_5", .addr = A_PPK0_5,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_6", .addr = A_PPK0_6,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_7", .addr = A_PPK0_7,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_8", .addr = A_PPK0_8,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_9", .addr = A_PPK0_9,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_10", .addr = A_PPK0_10,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK0_11", .addr = A_PPK0_11,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_0", .addr = A_PPK1_0,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_1", .addr = A_PPK1_1,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_2", .addr = A_PPK1_2,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_3", .addr = A_PPK1_3,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_4", .addr = A_PPK1_4,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_5", .addr = A_PPK1_5,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_6", .addr = A_PPK1_6,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_7", .addr = A_PPK1_7,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_8", .addr = A_PPK1_8,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_9", .addr = A_PPK1_9,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_10", .addr = A_PPK1_10,
|
||||
.ro = 0xffffffff,
|
||||
},{ .name = "PPK1_11", .addr = A_PPK1_11,
|
||||
.ro = 0xffffffff,
|
||||
}
|
||||
};
|
||||
|
||||
static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
RegisterInfoArray *reg_array = opaque;
|
||||
XlnxZynqMPEFuse *s;
|
||||
Object *dev;
|
||||
|
||||
assert(reg_array != NULL);
|
||||
|
||||
dev = reg_array->mem.owner;
|
||||
assert(dev);
|
||||
|
||||
s = XLNX_ZYNQMP_EFUSE(dev);
|
||||
|
||||
if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s[reg_0x%02lx]: Attempt to write locked register.\n",
|
||||
object_get_canonical_path(OBJECT(s)), (long)addr);
|
||||
} else {
|
||||
register_write_memory(opaque, addr, data, size);
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps zynqmp_efuse_ops = {
|
||||
.read = register_read_memory,
|
||||
.write = zynqmp_efuse_reg_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
|
||||
static void zynqmp_efuse_register_reset(RegisterInfo *reg)
|
||||
{
|
||||
if (!reg->data || !reg->access) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset must not trigger some registers' writers */
|
||||
switch (reg->access->addr) {
|
||||
case A_EFUSE_AES_CRC:
|
||||
*(uint32_t *)reg->data = reg->access->reset;
|
||||
return;
|
||||
}
|
||||
|
||||
register_reset(reg);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_reset(DeviceState *dev)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
|
||||
zynqmp_efuse_register_reset(&s->regs_info[i]);
|
||||
}
|
||||
|
||||
zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
|
||||
ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
|
||||
zynqmp_efuse_update_irq(s);
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
|
||||
|
||||
if (!s->efuse) {
|
||||
error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
|
||||
object_get_canonical_path(OBJECT(dev)));
|
||||
return;
|
||||
}
|
||||
|
||||
s->efuse->dev = dev;
|
||||
}
|
||||
|
||||
static void zynqmp_efuse_init(Object *obj)
|
||||
{
|
||||
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
RegisterInfoArray *reg_array;
|
||||
|
||||
reg_array =
|
||||
register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
|
||||
ARRAY_SIZE(zynqmp_efuse_regs_info),
|
||||
s->regs_info, s->regs,
|
||||
&zynqmp_efuse_ops,
|
||||
ZYNQMP_EFUSE_ERR_DEBUG,
|
||||
R_MAX * 4);
|
||||
|
||||
sysbus_init_mmio(sbd, ®_array->mem);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_efuse = {
|
||||
.name = TYPE_XLNX_ZYNQMP_EFUSE,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static Property zynqmp_efuse_props[] = {
|
||||
DEFINE_PROP_LINK("efuse",
|
||||
XlnxZynqMPEFuse, efuse,
|
||||
TYPE_XLNX_EFUSE, XlnxEFuse *),
|
||||
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = zynqmp_efuse_reset;
|
||||
dc->realize = zynqmp_efuse_realize;
|
||||
dc->vmsd = &vmstate_efuse;
|
||||
device_class_set_props(dc, zynqmp_efuse_props);
|
||||
}
|
||||
|
||||
|
||||
static const TypeInfo efuse_info = {
|
||||
.name = TYPE_XLNX_ZYNQMP_EFUSE,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XlnxZynqMPEFuse),
|
||||
.class_init = zynqmp_efuse_class_init,
|
||||
.instance_init = zynqmp_efuse_init,
|
||||
};
|
||||
|
||||
static void efuse_register_types(void)
|
||||
{
|
||||
type_register_static(&efuse_info);
|
||||
}
|
||||
|
||||
type_init(efuse_register_types)
|
||||
44
include/hw/nvram/xlnx-zynqmp-efuse.h
Normal file
44
include/hw/nvram/xlnx-zynqmp-efuse.h
Normal file
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Xilinx Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#ifndef XLNX_ZYNQMP_EFUSE_H
|
||||
#define XLNX_ZYNQMP_EFUSE_H
|
||||
|
||||
#include "hw/irq.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
#include "hw/nvram/xlnx-efuse.h"
|
||||
|
||||
#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
|
||||
|
||||
#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE);
|
||||
|
||||
struct XlnxZynqMPEFuse {
|
||||
SysBusDevice parent_obj;
|
||||
qemu_irq irq;
|
||||
|
||||
XlnxEFuse *efuse;
|
||||
uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
|
||||
RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user