hw/intc/bcm2836_control: Implement local timer
The BCM2836 control logic module includes a simple "local timer" which is a programmable down-counter that can generates an interrupt. Implement this functionality. Signed-off-by: Zoltán Baldaszti <bztemail@gmail.com> [PMM: wrote commit message; wrapped long line; tweaked some comments to match the final version of the code] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -7,7 +7,9 @@
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* This code is licensed under the GNU GPLv2 and later.
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*
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* At present, only implements interrupt routing, and mailboxes (i.e.,
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* not local timer, PMU interrupt, or AXI counters).
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* not PMU interrupt, or AXI counters).
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*
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* ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
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*
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* Ref:
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* https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
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@ -18,6 +20,9 @@
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#include "qemu/log.h"
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#define REG_GPU_ROUTE 0x0c
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#define REG_LOCALTIMERROUTING 0x24
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#define REG_LOCALTIMERCONTROL 0x34
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#define REG_LOCALTIMERACK 0x38
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#define REG_TIMERCONTROL 0x40
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#define REG_MBOXCONTROL 0x50
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#define REG_IRQSRC 0x60
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@ -43,6 +48,13 @@
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#define IRQ_TIMER 11
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#define IRQ_MAX IRQ_TIMER
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#define LOCALTIMER_FREQ 38400000
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#define LOCALTIMER_INTFLAG (1 << 31)
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#define LOCALTIMER_RELOAD (1 << 30)
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#define LOCALTIMER_INTENABLE (1 << 29)
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#define LOCALTIMER_ENABLE (1 << 28)
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#define LOCALTIMER_VALUE(x) ((x) & 0xfffffff)
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static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
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uint32_t controlreg, uint8_t controlidx)
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{
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@ -78,6 +90,20 @@ static void bcm2836_control_update(BCM2836ControlState *s)
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s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
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}
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/*
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* handle the control module 'local timer' interrupt for one of the
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* cores' IRQ/FIQ; this is distinct from the per-CPU timer
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* interrupts handled below.
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*/
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if ((s->local_timer_control & LOCALTIMER_INTENABLE) &&
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(s->local_timer_control & LOCALTIMER_INTFLAG)) {
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if (s->route_localtimer & 4) {
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s->fiqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
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} else {
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s->irqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
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}
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}
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for (i = 0; i < BCM2836_NCORES; i++) {
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/* handle local timer interrupts for this core */
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if (s->timerirqs[i]) {
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@ -162,6 +188,54 @@ static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level)
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bcm2836_control_update(s);
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}
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static void bcm2836_control_local_timer_set_next(void *opaque)
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{
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BCM2836ControlState *s = opaque;
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uint64_t next_event;
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assert(LOCALTIMER_VALUE(s->local_timer_control) > 0);
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next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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muldiv64(LOCALTIMER_VALUE(s->local_timer_control),
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NANOSECONDS_PER_SECOND, LOCALTIMER_FREQ);
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timer_mod(&s->timer, next_event);
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}
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static void bcm2836_control_local_timer_tick(void *opaque)
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{
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BCM2836ControlState *s = opaque;
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bcm2836_control_local_timer_set_next(s);
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s->local_timer_control |= LOCALTIMER_INTFLAG;
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bcm2836_control_update(s);
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}
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static void bcm2836_control_local_timer_control(void *opaque, uint32_t val)
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{
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BCM2836ControlState *s = opaque;
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s->local_timer_control = val;
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if (val & LOCALTIMER_ENABLE) {
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bcm2836_control_local_timer_set_next(s);
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} else {
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timer_del(&s->timer);
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}
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}
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static void bcm2836_control_local_timer_ack(void *opaque, uint32_t val)
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{
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BCM2836ControlState *s = opaque;
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if (val & LOCALTIMER_INTFLAG) {
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s->local_timer_control &= ~LOCALTIMER_INTFLAG;
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}
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if ((val & LOCALTIMER_RELOAD) &&
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(s->local_timer_control & LOCALTIMER_ENABLE)) {
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bcm2836_control_local_timer_set_next(s);
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}
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}
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static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2836ControlState *s = opaque;
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@ -170,6 +244,12 @@ static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
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assert(s->route_gpu_fiq < BCM2836_NCORES
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&& s->route_gpu_irq < BCM2836_NCORES);
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return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
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} else if (offset == REG_LOCALTIMERROUTING) {
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return s->route_localtimer;
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} else if (offset == REG_LOCALTIMERCONTROL) {
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return s->local_timer_control;
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} else if (offset == REG_LOCALTIMERACK) {
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return 0;
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} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
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return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
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} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
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@ -195,6 +275,12 @@ static void bcm2836_control_write(void *opaque, hwaddr offset,
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if (offset == REG_GPU_ROUTE) {
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s->route_gpu_irq = val & 0x3;
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s->route_gpu_fiq = (val >> 2) & 0x3;
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} else if (offset == REG_LOCALTIMERROUTING) {
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s->route_localtimer = val & 7;
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} else if (offset == REG_LOCALTIMERCONTROL) {
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bcm2836_control_local_timer_control(s, val);
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} else if (offset == REG_LOCALTIMERACK) {
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bcm2836_control_local_timer_ack(s, val);
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} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
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s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
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} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
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@ -227,6 +313,10 @@ static void bcm2836_control_reset(DeviceState *d)
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s->route_gpu_irq = s->route_gpu_fiq = 0;
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timer_del(&s->timer);
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s->route_localtimer = 0;
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s->local_timer_control = 0;
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for (i = 0; i < BCM2836_NCORES; i++) {
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s->timercontrol[i] = 0;
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s->mailboxcontrol[i] = 0;
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@ -263,11 +353,15 @@ static void bcm2836_control_init(Object *obj)
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/* outputs to CPU cores */
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qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
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qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
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/* create a qemu virtual timer */
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timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL,
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bcm2836_control_local_timer_tick, s);
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}
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static const VMStateDescription vmstate_bcm2836_control = {
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.name = TYPE_BCM2836_CONTROL,
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
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@ -277,6 +371,9 @@ static const VMStateDescription vmstate_bcm2836_control = {
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VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
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VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
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BCM2836_NCORES),
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VMSTATE_TIMER_V(timer, BCM2836ControlState, 2),
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VMSTATE_UINT32_V(local_timer_control, BCM2836ControlState, 2),
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VMSTATE_UINT8_V(route_localtimer, BCM2836ControlState, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -5,6 +5,9 @@
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
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* Added basic IRQ_TIMER interrupt support
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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@ -12,6 +15,7 @@
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#define BCM2836_CONTROL_H
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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/* 4 mailboxes per core, for 16 total */
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#define BCM2836_NCORES 4
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@ -39,6 +43,11 @@ typedef struct BCM2836ControlState {
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bool gpu_irq, gpu_fiq;
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uint8_t timerirqs[BCM2836_NCORES];
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/* local timer */
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QEMUTimer timer;
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uint32_t local_timer_control;
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uint8_t route_localtimer;
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/* interrupt source registers, post-routing (also input-derived; visible) */
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uint32_t irqsrc[BCM2836_NCORES];
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uint32_t fiqsrc[BCM2836_NCORES];
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