hw/block/nvme: report non-mdts command size limit for dsm
Dataset Management is not subject to MDTS, but exceeded a certain size per range causes internal looping. Report this limit (DMRSL) in the NVM command set specific identify controller data structure. Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
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@ -1789,6 +1789,10 @@ static uint16_t nvme_dsm(NvmeCtrl *n, NvmeRequest *req)
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trace_pci_nvme_dsm_deallocate(nvme_cid(req), nvme_nsid(ns), slba,
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nlb);
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if (nlb > n->dmrsl) {
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trace_pci_nvme_dsm_single_range_limit_exceeded(nlb, n->dmrsl);
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}
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offset = nvme_l2b(ns, slba);
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len = nvme_l2b(ns, nlb);
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@ -3208,20 +3212,24 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
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static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req)
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{
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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NvmeIdCtrlZoned id = {};
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uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {};
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trace_pci_nvme_identify_ctrl_csi(c->csi);
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if (c->csi == NVME_CSI_NVM) {
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return nvme_rpt_empty_id_struct(n, req);
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} else if (c->csi == NVME_CSI_ZONED) {
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id.zasl = n->params.zasl;
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switch (c->csi) {
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case NVME_CSI_NVM:
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((NvmeIdCtrlNvm *)&id)->dmrsl = cpu_to_le32(n->dmrsl);
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break;
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return nvme_dma(n, (uint8_t *)&id, sizeof(id),
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DMA_DIRECTION_FROM_DEVICE, req);
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case NVME_CSI_ZONED:
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((NvmeIdCtrlZoned *)&id)->zasl = n->params.zasl;
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break;
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default:
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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return NVME_INVALID_FIELD | NVME_DNR;
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return nvme_dma(n, id, sizeof(id), DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
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@ -4655,6 +4663,9 @@ int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
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n->namespaces[nsid - 1] = ns;
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n->dmrsl = MIN_NON_ZERO(n->dmrsl,
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BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
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return 0;
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}
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@ -171,6 +171,8 @@ typedef struct NvmeCtrl {
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QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
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int aer_queued;
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uint32_t dmrsl;
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NvmeSubsystem *subsys;
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NvmeNamespace namespace;
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@ -51,6 +51,7 @@ pci_nvme_copy_cb(uint16_t cid) "cid %"PRIu16""
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pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret, bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x zeroed %d"
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pci_nvme_dsm(uint16_t cid, uint32_t nsid, uint32_t nr, uint32_t attr) "cid %"PRIu16" nsid %"PRIu32" nr %"PRIu32" attr 0x%"PRIx32""
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pci_nvme_dsm_deallocate(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32""
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pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl) "nlb %"PRIu32" dmrsl %"PRIu32""
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pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32""
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pci_nvme_compare_cb(uint16_t cid) "cid %"PRIu16""
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pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16""
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@ -1041,6 +1041,16 @@ typedef struct NvmeIdCtrlZoned {
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uint8_t rsvd1[4095];
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} NvmeIdCtrlZoned;
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typedef struct NvmeIdCtrlNvm {
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uint8_t vsl;
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uint8_t wzsl;
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uint8_t wusl;
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uint8_t dmrl;
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uint32_t dmrsl;
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uint64_t dmsl;
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uint8_t rsvd16[4080];
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} NvmeIdCtrlNvm;
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enum NvmeIdCtrlOacs {
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NVME_OACS_SECURITY = 1 << 0,
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NVME_OACS_FORMAT = 1 << 1,
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@ -1396,6 +1406,7 @@ static inline void _nvme_check_size(void)
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QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096);
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QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096);
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QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096);
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QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096);
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QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4);
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QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16);
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QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
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