hw/arm/smmu: Refactor SMMU OAS
SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested configurations that can be a problem, as stage-2 might be shared with the CPU which might have different PARANGE, and according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. This patch doesn't change the SMMU OAS, but refactors the code to make it easier to do that: - Rely everywhere on IDR5 for reading OAS instead of using the SMMU_IDR5_OAS macro, so, it is easier just to change IDR5 and it propagages correctly. - Add additional checks when OAS is greater than 48bits. - Remove unused functions/macros: pa_range/MAX_PA. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20240715084519.1189624-19-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -452,7 +452,8 @@ static int smmu_ptw_64_s1(SMMUState *bs, SMMUTransCfg *cfg,
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inputsize = 64 - tt->tsz;
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level = 4 - (inputsize - 4) / stride;
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indexmask = VMSA_IDXMSK(inputsize, stride, level);
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baseaddr = extract64(tt->ttb, 0, 48);
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baseaddr = extract64(tt->ttb, 0, cfg->oas);
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baseaddr &= ~indexmask;
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while (level < VMSA_LEVELS) {
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@ -576,8 +577,8 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
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* Get the ttb from concatenated structure.
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* The offset is the idx * size of each ttb(number of ptes * (sizeof(pte))
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*/
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uint64_t baseaddr = extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride) *
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idx * sizeof(uint64_t);
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uint64_t baseaddr = extract64(cfg->s2cfg.vttb, 0, cfg->s2cfg.eff_ps) +
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(1 << stride) * idx * sizeof(uint64_t);
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dma_addr_t indexmask = VMSA_IDXMSK(inputsize, stride, level);
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baseaddr &= ~indexmask;
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@ -602,19 +602,6 @@ static inline int oas2bits(int oas_field)
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return -1;
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}
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static inline int pa_range(STE *ste)
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{
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int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
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if (!STE_S2AA64(ste)) {
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return 40;
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}
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return oas2bits(oas_field);
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}
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#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
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/* CD fields */
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#define CD_VALID(x) extract32((x)->word[0], 31, 1)
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@ -402,10 +402,10 @@ static bool s2t0sz_valid(SMMUTransCfg *cfg)
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}
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if (cfg->s2cfg.granule_sz == 16) {
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return (cfg->s2cfg.tsz >= 64 - oas2bits(SMMU_IDR5_OAS));
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return (cfg->s2cfg.tsz >= 64 - cfg->s2cfg.eff_ps);
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}
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return (cfg->s2cfg.tsz >= MAX(64 - oas2bits(SMMU_IDR5_OAS), 16));
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return (cfg->s2cfg.tsz >= MAX(64 - cfg->s2cfg.eff_ps, 16));
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}
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/*
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@ -426,8 +426,11 @@ static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran)
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return nr_concat <= VMSA_MAX_S2_CONCAT;
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}
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static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
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static int decode_ste_s2_cfg(SMMUv3State *s, SMMUTransCfg *cfg,
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STE *ste)
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{
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uint8_t oas = FIELD_EX32(s->idr[5], IDR5, OAS);
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if (STE_S2AA64(ste) == 0x0) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 AArch32 tables not supported\n");
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@ -460,7 +463,15 @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
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}
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/* For AA64, The effective S2PS size is capped to the OAS. */
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cfg->s2cfg.eff_ps = oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS));
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cfg->s2cfg.eff_ps = oas2bits(MIN(STE_S2PS(ste), oas));
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/*
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* For SMMUv3.1 and later, when OAS == IAS == 52, the stage 2 input
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* range is further limited to 48 bits unless STE.S2TG indicates a
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* 64KB granule.
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*/
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if (cfg->s2cfg.granule_sz != 16) {
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cfg->s2cfg.eff_ps = MIN(cfg->s2cfg.eff_ps, 48);
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}
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/*
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* It is ILLEGAL for the address in S2TTB to be outside the range
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* described by the effective S2PS value.
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@ -536,6 +547,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
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STE *ste, SMMUEventInfo *event)
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{
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uint32_t config;
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uint8_t oas = FIELD_EX32(s->idr[5], IDR5, OAS);
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int ret;
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if (!STE_VALID(ste)) {
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@ -579,8 +591,8 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
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* Stage-1 OAS defaults to OAS even if not enabled as it would be used
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* in input address check for stage-2.
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*/
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cfg->oas = oas2bits(SMMU_IDR5_OAS);
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ret = decode_ste_s2_cfg(cfg, ste);
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cfg->oas = oas2bits(oas);
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ret = decode_ste_s2_cfg(s, cfg, ste);
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if (ret) {
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goto bad_ste;
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}
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@ -706,6 +718,7 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg,
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int i;
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SMMUTranslationStatus status;
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SMMUTLBEntry *entry;
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uint8_t oas = FIELD_EX32(s->idr[5], IDR5, OAS);
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if (!CD_VALID(cd) || !CD_AARCH64(cd)) {
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goto bad_cd;
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@ -724,7 +737,7 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg,
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cfg->aa64 = true;
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cfg->oas = oas2bits(CD_IPS(cd));
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cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
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cfg->oas = MIN(oas2bits(oas), cfg->oas);
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cfg->tbi = CD_TBI(cd);
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cfg->asid = CD_ASID(cd);
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cfg->affd = CD_AFFD(cd);
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@ -753,6 +766,14 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg,
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goto bad_cd;
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}
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/*
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* An address greater than 48 bits in size can only be output from a
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* TTD when, in SMMUv3.1 and later, the effective IPS is 52 and a 64KB
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* granule is in use for that translation table
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*/
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if (tt->granule_sz != 16) {
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cfg->oas = MIN(cfg->oas, 48);
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}
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tt->tsz = tsz;
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tt->ttb = CD_TTB(cd, i);
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