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cpu: Move ENV_OFFSET to exec/gen-icount.h

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Now that we have ArchCPU, we can define this generically,
in the one place that needs it.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-03-22 17:00:56 -07:00
parent 92fddfbd17
commit 677c4d69ac
22 changed files with 2 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/exec/gen-icount.h
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@ -5,6 +5,8 @@
/* Helpers for instruction counting code generation. */ /* Helpers for instruction counting code generation. */
#define ENV_OFFSET offsetof(ArchCPU, env)
static TCGOp *icount_start_insn; static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb) static inline void gen_tb_start(TranslationBlock *tb)

1
target/alpha/cpu.h
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@ -278,7 +278,6 @@ struct AlphaCPU {
QEMUTimer *alarm_timer; QEMUTimer *alarm_timer;
}; };
#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_alpha_cpu; extern const struct VMStateDescription vmstate_alpha_cpu;

2
target/arm/cpu.h
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@ -917,8 +917,6 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#define ENV_OFFSET offsetof(ARMCPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_arm_cpu; extern const struct VMStateDescription vmstate_arm_cpu;
#endif #endif

1
target/cris/cpu.h
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@ -183,7 +183,6 @@ struct CRISCPU {
CPUCRISState env; CPUCRISState env;
}; };
#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_cris_cpu; extern const struct VMStateDescription vmstate_cris_cpu;

1
target/hppa/cpu.h
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@ -222,7 +222,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer; QEMUTimer *alarm_timer;
}; };
#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState; typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU; typedef HPPACPU ArchCPU;

1
target/i386/cpu.h
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@ -1480,7 +1480,6 @@ struct X86CPU {
int32_t hv_max_vps; int32_t hv_max_vps;
}; };
#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern struct VMStateDescription vmstate_x86_cpu; extern struct VMStateDescription vmstate_x86_cpu;

1
target/lm32/cpu.h
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@ -195,7 +195,6 @@ struct LM32CPU {
uint32_t features; uint32_t features;
}; };
#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_lm32_cpu; extern const struct VMStateDescription vmstate_lm32_cpu;

1
target/m68k/cpu.h
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@ -163,7 +163,6 @@ struct M68kCPU {
CPUM68KState env; CPUM68KState env;
}; };
#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu); void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);

1
target/microblaze/cpu.h
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@ -310,7 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env; CPUMBState env;
}; };
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs); void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);

1
target/mips/cpu.h
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@ -1071,7 +1071,6 @@ struct MIPSCPU {
CPUMIPSState env; CPUMIPSState env;
}; };
#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list(void); void mips_cpu_list(void);

1
target/moxie/cpu.h
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@ -90,7 +90,6 @@ typedef struct MoxieCPU {
CPUMoxieState env; CPUMoxieState env;
} MoxieCPU; } MoxieCPU;
#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs); void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

1
target/nios2/cpu.h
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@ -194,7 +194,6 @@ typedef struct Nios2CPU {
uint32_t fast_tlb_miss_addr; uint32_t fast_tlb_miss_addr;
} Nios2CPU; } Nios2CPU;
#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void); void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs); void nios2_cpu_do_interrupt(CPUState *cs);

1
target/openrisc/cpu.h
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@ -317,7 +317,6 @@ typedef struct OpenRISCCPU {
} OpenRISCCPU; } OpenRISCCPU;
#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(void); void cpu_openrisc_list(void);
void openrisc_cpu_do_interrupt(CPUState *cpu); void openrisc_cpu_do_interrupt(CPUState *cpu);

1
target/ppc/cpu.h
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@ -1203,7 +1203,6 @@ struct PowerPCCPU {
int32_t mig_slb_nr; int32_t mig_slb_nr;
}; };
#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);

2
target/riscv/cpu.h
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@ -239,8 +239,6 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[]; extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[]; extern const char * const riscv_intr_names[];
#define ENV_OFFSET offsetof(RISCVCPU, env)
void riscv_cpu_do_interrupt(CPUState *cpu); void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

1
target/s390x/cpu.h
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@ -163,7 +163,6 @@ struct S390CPU {
uint32_t irqstate_saved_size; uint32_t irqstate_saved_size;
}; };
#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_s390_cpu; extern const struct VMStateDescription vmstate_s390_cpu;

1
target/sh4/cpu.h
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@ -207,7 +207,6 @@ struct SuperHCPU {
CPUSH4State env; CPUSH4State env;
}; };
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu); void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);

1
target/sparc/cpu.h
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@ -532,7 +532,6 @@ struct SPARCCPU {
CPUSPARCState env; CPUSPARCState env;
}; };
#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_sparc_cpu; extern const struct VMStateDescription vmstate_sparc_cpu;

1
target/tilegx/cpu.h
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@ -138,7 +138,6 @@ typedef struct TileGXCPU {
CPUTLGState env; CPUTLGState env;
} TileGXCPU; } TileGXCPU;
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */ /* TILE-Gx memory attributes */
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */

1
target/tricore/cpu.h
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@ -208,7 +208,6 @@ struct TriCoreCPU {
CPUTriCoreState env; CPUTriCoreState env;
}; };
#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

1
target/unicore32/cpu.h
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@ -76,7 +76,6 @@ struct UniCore32CPU {
CPUUniCore32State env; CPUUniCore32State env;
}; };
#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu); void uc32_cpu_do_interrupt(CPUState *cpu);
bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);

2
target/xtensa/cpu.h
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@ -559,8 +559,6 @@ struct XtensaCPU {
CPUXtensaState env; CPUXtensaState env;
}; };
#define ENV_OFFSET offsetof(XtensaCPU, env)
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx, MMUAccessType access_type, int mmu_idx,