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hw/pci: add PCI resource reserve capability to legacy PCI bridge

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Add hint to firmware (e.g. SeaBIOS) to reserve addtional
BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
resource reserve capability deleting in pci_bridge_dev_exitfn.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jing Liu 2018-08-21 11:18:07 +08:00 committed by Michael S. Tsirkin
parent 9e8993991e
commit 6755e618d0
1 changed files with 24 additions and 0 deletions
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24
hw/pci-bridge/pci_bridge_dev.c
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@ -46,6 +46,9 @@ struct PCIBridgeDev {
uint32_t flags; uint32_t flags;
OnOffAuto msi; OnOffAuto msi;
/* additional resources to reserve */
PCIResReserve res_reserve;
}; };
typedef struct PCIBridgeDev PCIBridgeDev; typedef struct PCIBridgeDev PCIBridgeDev;
@ -95,6 +98,12 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
error_free(local_err); error_free(local_err);
} }
err = pci_bridge_qemu_reserve_cap_init(dev, 0,
bridge_dev->res_reserve, errp);
if (err) {
goto cap_error;
}
if (shpc_present(dev)) { if (shpc_present(dev)) {
/* TODO: spec recommends using 64 bit prefetcheable BAR. /* TODO: spec recommends using 64 bit prefetcheable BAR.
* Check whether that works well. */ * Check whether that works well. */
@ -103,6 +112,8 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
} }
return; return;
cap_error:
msi_uninit(dev);
msi_error: msi_error:
slotid_cap_cleanup(dev); slotid_cap_cleanup(dev);
slotid_error: slotid_error:
@ -116,6 +127,8 @@ shpc_error:
static void pci_bridge_dev_exitfn(PCIDevice *dev) static void pci_bridge_dev_exitfn(PCIDevice *dev)
{ {
PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev); PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap));
if (msi_present(dev)) { if (msi_present(dev)) {
msi_uninit(dev); msi_uninit(dev);
} }
@ -162,6 +175,17 @@ static Property pci_bridge_dev_properties[] = {
ON_OFF_AUTO_AUTO), ON_OFF_AUTO_AUTO),
DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags,
PCI_BRIDGE_DEV_F_SHPC_REQ, true), PCI_BRIDGE_DEV_F_SHPC_REQ, true),
DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev,
res_reserve.bus, -1),
DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev,
res_reserve.io, -1),
DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev,
res_reserve.mem_non_pref, -1),
DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev,
res_reserve.mem_pref_32, -1),
DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev,
res_reserve.mem_pref_64, -1),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };