mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg-s390: Remove W constraint

Browse Source 
Now redundant with the type parameter to tcg_target_const_match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-03-31 02:25:26 -04:00
parent 4b304cfae1
commit 671c835b7d
1 changed files with 19 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
tcg/s390/tcg-target.c
View File

@ -38,11 +38,10 @@
a 32-bit displacement here Just In Case. */ a 32-bit displacement here Just In Case. */
#define USE_LONG_BRANCHES 0 #define USE_LONG_BRANCHES 0
#define TCG_CT_CONST_32 0x0100 #define TCG_CT_CONST_MULI 0x100
#define TCG_CT_CONST_MULI 0x0800 #define TCG_CT_CONST_ORI 0x200
#define TCG_CT_CONST_ORI 0x2000 #define TCG_CT_CONST_XORI 0x400
#define TCG_CT_CONST_XORI 0x4000 #define TCG_CT_CONST_CMPI 0x800
#define TCG_CT_CONST_CMPI 0x8000
/* Several places within the instruction set 0 means "no register" /* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0. */ rather than TCG_REG_R0. */
@ -407,9 +406,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_clear(ct->u.regs); tcg_regset_clear(ct->u.regs);
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
break; break;
case 'W': /* force 32-bit ("word") immediate */
ct->ct |= TCG_CT_CONST_32;
break;
case 'K': case 'K':
ct->ct |= TCG_CT_CONST_MULI; ct->ct |= TCG_CT_CONST_MULI;
break; break;
@ -437,10 +433,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
can load efficiently, and the immediate load plus the reg-reg OR is can load efficiently, and the immediate load plus the reg-reg OR is
smaller than the sequential OI's. */ smaller than the sequential OI's. */
static int tcg_match_ori(int ct, tcg_target_long val) static int tcg_match_ori(TCGType type, tcg_target_long val)
{ {
if (facilities & FACILITY_EXT_IMM) { if (facilities & FACILITY_EXT_IMM) {
if (ct & TCG_CT_CONST_32) { if (type == TCG_TYPE_I32) {
/* All 32-bit ORs can be performed with 1 48-bit insn. */ /* All 32-bit ORs can be performed with 1 48-bit insn. */
return 1; return 1;
} }
@ -466,13 +462,13 @@ static int tcg_match_ori(int ct, tcg_target_long val)
extended-immediate facility. That said, there are a few patterns for extended-immediate facility. That said, there are a few patterns for
which it is better to load the value into a register first. */ which it is better to load the value into a register first. */
static int tcg_match_xori(int ct, tcg_target_long val) static int tcg_match_xori(TCGType type, tcg_target_long val)
{ {
if ((facilities & FACILITY_EXT_IMM) == 0) { if ((facilities & FACILITY_EXT_IMM) == 0) {
return 0; return 0;
} }
if (ct & TCG_CT_CONST_32) { if (type == TCG_TYPE_I32) {
/* All 32-bit XORs can be performed with 1 48-bit insn. */ /* All 32-bit XORs can be performed with 1 48-bit insn. */
return 1; return 1;
} }
@ -487,11 +483,11 @@ static int tcg_match_xori(int ct, tcg_target_long val)
/* Imediates to be used with comparisons. */ /* Imediates to be used with comparisons. */
static int tcg_match_cmpi(int ct, tcg_target_long val) static int tcg_match_cmpi(TCGType type, tcg_target_long val)
{ {
if (facilities & FACILITY_EXT_IMM) { if (facilities & FACILITY_EXT_IMM) {
/* The COMPARE IMMEDIATE instruction is available. */ /* The COMPARE IMMEDIATE instruction is available. */
if (ct & TCG_CT_CONST_32) { if (type == TCG_TYPE_I32) {
/* We have a 32-bit immediate and can compare against anything. */ /* We have a 32-bit immediate and can compare against anything. */
return 1; return 1;
} else { } else {
@ -524,8 +520,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
return 1; return 1;
} }
/* Handle the modifiers. */ if (type == TCG_TYPE_I32) {
if (ct & TCG_CT_CONST_32) {
val = (int32_t)val; val = (int32_t)val;
} }
@ -541,11 +536,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
return val == (int16_t)val; return val == (int16_t)val;
} }
} else if (ct & TCG_CT_CONST_ORI) { } else if (ct & TCG_CT_CONST_ORI) {
return tcg_match_ori(ct, val); return tcg_match_ori(type, val);
} else if (ct & TCG_CT_CONST_XORI) { } else if (ct & TCG_CT_CONST_XORI) {
return tcg_match_xori(ct, val); return tcg_match_xori(type, val);
} else if (ct & TCG_CT_CONST_CMPI) { } else if (ct & TCG_CT_CONST_CMPI) {
return tcg_match_cmpi(ct, val); return tcg_match_cmpi(type, val);
} }
return 0; return 0;
@ -2112,8 +2107,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } },
{ INDEX_op_and_i32, { "r", "0", "ri" } }, { INDEX_op_and_i32, { "r", "0", "ri" } },
{ INDEX_op_or_i32, { "r", "0", "rWO" } }, { INDEX_op_or_i32, { "r", "0", "rO" } },
{ INDEX_op_xor_i32, { "r", "0", "rWX" } }, { INDEX_op_xor_i32, { "r", "0", "rX" } },
{ INDEX_op_neg_i32, { "r", "r" } }, { INDEX_op_neg_i32, { "r", "r" } },
@ -2135,9 +2130,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "r", "r" } }, { INDEX_op_add2_i32, { "r", "r", "0", "1", "r", "r" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "r", "r" } }, { INDEX_op_sub2_i32, { "r", "r", "0", "1", "r", "r" } },
{ INDEX_op_brcond_i32, { "r", "rWC" } }, { INDEX_op_brcond_i32, { "r", "rC" } },
{ INDEX_op_setcond_i32, { "r", "r", "rWC" } }, { INDEX_op_setcond_i32, { "r", "r", "rC" } },
{ INDEX_op_movcond_i32, { "r", "r", "rWC", "r", "0" } }, { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } },
{ INDEX_op_deposit_i32, { "r", "0", "r" } }, { INDEX_op_deposit_i32, { "r", "0", "r" } },
{ INDEX_op_qemu_ld8u, { "r", "L" } }, { INDEX_op_qemu_ld8u, { "r", "L" } },