i.MX: Rework functions/types name and use new style initialization
* use dynamic cast whenever possible * Change function names to some more meaningful prefix * Change type names to a more meaningful one * use new style device initialization Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1369898943-1993-3-git-send-email-jcd@tribudubois.net Reviewed-by: Peter Chubb <peter.chubb@nicta.com.au> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe DUBOIS
Peter Maydell
parent
5ec694b52a
commit
67110c3e01
@ -27,7 +27,7 @@
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#define DEBUG_TIMER 0
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#if DEBUG_TIMER
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static char const *imx_timerg_reg_name(uint32_t reg)
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static char const *imx_gpt_reg_name(uint32_t reg)
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{
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switch (reg) {
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case 0:
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@ -67,12 +67,14 @@ static char const *imx_timerg_reg_name(uint32_t reg)
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*/
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#define DEBUG_IMPLEMENTATION 1
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#if DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
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#else
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# define IPRINTF(fmt, args...) do {} while (0)
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#endif
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#define IMX_GPT(obj) \
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OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
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/*
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* GPT : General purpose timer
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*
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@ -137,33 +139,33 @@ typedef struct {
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uint32_t freq;
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qemu_irq irq;
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} IMXTimerGState;
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} IMXGPTState;
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static const VMStateDescription vmstate_imx_timerg = {
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static const VMStateDescription vmstate_imx_timer_gpt = {
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.name = TYPE_IMX_GPT,
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXTimerGState),
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VMSTATE_UINT32(pr, IMXTimerGState),
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VMSTATE_UINT32(sr, IMXTimerGState),
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VMSTATE_UINT32(ir, IMXTimerGState),
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VMSTATE_UINT32(ocr1, IMXTimerGState),
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VMSTATE_UINT32(ocr2, IMXTimerGState),
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VMSTATE_UINT32(ocr3, IMXTimerGState),
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VMSTATE_UINT32(icr1, IMXTimerGState),
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VMSTATE_UINT32(icr2, IMXTimerGState),
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VMSTATE_UINT32(cnt, IMXTimerGState),
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VMSTATE_UINT32(next_timeout, IMXTimerGState),
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VMSTATE_UINT32(next_int, IMXTimerGState),
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VMSTATE_UINT32(freq, IMXTimerGState),
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VMSTATE_PTIMER(timer, IMXTimerGState),
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VMSTATE_UINT32(cr, IMXGPTState),
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VMSTATE_UINT32(pr, IMXGPTState),
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VMSTATE_UINT32(sr, IMXGPTState),
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VMSTATE_UINT32(ir, IMXGPTState),
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VMSTATE_UINT32(ocr1, IMXGPTState),
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VMSTATE_UINT32(ocr2, IMXGPTState),
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VMSTATE_UINT32(ocr3, IMXGPTState),
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VMSTATE_UINT32(icr1, IMXGPTState),
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VMSTATE_UINT32(icr2, IMXGPTState),
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VMSTATE_UINT32(cnt, IMXGPTState),
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VMSTATE_UINT32(next_timeout, IMXGPTState),
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VMSTATE_UINT32(next_int, IMXGPTState),
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VMSTATE_UINT32(freq, IMXGPTState),
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VMSTATE_PTIMER(timer, IMXGPTState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const IMXClk imx_timerg_clocks[] = {
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static const IMXClk imx_gpt_clocks[] = {
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NOCLK, /* 000 No clock source */
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IPG, /* 001 ipg_clk, 532MHz*/
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IPG, /* 010 ipg_clk_highfreq */
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@ -174,10 +176,10 @@ static const IMXClk imx_timerg_clocks[] = {
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NOCLK, /* 111 not defined */
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};
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static void imx_timerg_set_freq(IMXTimerGState *s)
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static void imx_gpt_set_freq(IMXGPTState *s)
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{
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uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
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uint32_t freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc])
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uint32_t freq = imx_clock_frequency(s->ccm, imx_gpt_clocks[clksrc])
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/ (1 + s->pr);
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s->freq = freq;
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@ -188,7 +190,7 @@ static void imx_timerg_set_freq(IMXTimerGState *s)
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}
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}
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static void imx_timerg_update(IMXTimerGState *s)
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static void imx_gpt_update_int(IMXGPTState *s)
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{
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if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
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qemu_irq_raise(s->irq);
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@ -197,14 +199,14 @@ static void imx_timerg_update(IMXTimerGState *s)
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}
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}
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static uint32_t imx_timerg_update_counts(IMXTimerGState *s)
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static uint32_t imx_gpt_update_count(IMXGPTState *s)
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{
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s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
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return s->cnt;
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}
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static inline uint32_t imx_timerg_find_limit(uint32_t count, uint32_t reg,
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static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
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uint32_t timeout)
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{
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if ((count < reg) && (timeout > reg)) {
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@ -214,7 +216,7 @@ static inline uint32_t imx_timerg_find_limit(uint32_t count, uint32_t reg,
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return timeout;
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}
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static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event)
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static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
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{
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uint32_t timeout = TIMER_MAX;
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uint32_t count = 0;
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@ -233,24 +235,24 @@ static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event)
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* if we are in free running mode and we have not reached
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* the TIMER_MAX limit, then update the count
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*/
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count = imx_timerg_update_counts(s);
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count = imx_gpt_update_count(s);
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}
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} else {
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/* not a timer event, then just update the count */
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count = imx_timerg_update_counts(s);
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count = imx_gpt_update_count(s);
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}
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/* now, find the next timeout related to count */
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if (s->ir & GPT_IR_OF1IE) {
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timeout = imx_timerg_find_limit(count, s->ocr1, timeout);
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timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
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}
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if (s->ir & GPT_IR_OF2IE) {
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timeout = imx_timerg_find_limit(count, s->ocr2, timeout);
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timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
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}
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if (s->ir & GPT_IR_OF3IE) {
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timeout = imx_timerg_find_limit(count, s->ocr3, timeout);
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timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
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}
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/* find the next set of interrupts to raise for next timer event */
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@ -270,7 +272,7 @@ static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event)
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}
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/* the new range to count down from */
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limit = timeout - imx_timerg_update_counts(s);
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limit = timeout - imx_gpt_update_count(s);
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if (limit < 0) {
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/*
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@ -280,9 +282,9 @@ static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event)
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*/
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s->sr |= s->next_int;
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imx_timerg_compute_next_timeout(s, event);
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imx_gpt_compute_next_timeout(s, event);
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imx_timerg_update(s);
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imx_gpt_update_int(s);
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} else {
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/* New timeout value */
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s->next_timeout = timeout;
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@ -292,10 +294,9 @@ static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event)
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}
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}
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static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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unsigned size)
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static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t reg_value = 0;
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uint32_t reg = offset >> 2;
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@ -339,7 +340,7 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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break;
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case 9: /* cnt */
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imx_timerg_update_counts(s);
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imx_gpt_update_count(s);
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reg_value = s->cnt;
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break;
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@ -348,14 +349,14 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
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break;
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}
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DPRINTF("(%s) = 0x%08x\n", imx_timerg_reg_name(reg), reg_value);
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DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value);
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return reg_value;
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}
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static void imx_timerg_reset(DeviceState *dev)
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static void imx_gpt_reset(DeviceState *dev)
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{
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IMXTimerGState *s = container_of(dev, IMXTimerGState, busdev.qdev);
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IMXGPTState *s = IMX_GPT(dev);
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/* stop timer */
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ptimer_stop(s->timer);
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@ -379,7 +380,7 @@ static void imx_timerg_reset(DeviceState *dev)
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s->next_int = 0;
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/* compute new freq */
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imx_timerg_set_freq(s);
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imx_gpt_set_freq(s);
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/* reset the limit to TIMER_MAX */
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ptimer_set_limit(s->timer, TIMER_MAX, 1);
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@ -390,14 +391,14 @@ static void imx_timerg_reset(DeviceState *dev)
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}
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}
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static void imx_timerg_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t oldreg;
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uint32_t reg = offset >> 2;
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DPRINTF("(%s, value = 0x%08x)\n", imx_timerg_reg_name(reg),
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DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg),
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(uint32_t)value);
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switch (reg) {
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@ -406,17 +407,17 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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s->cr = value & ~0x7c14;
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if (s->cr & GPT_CR_SWR) { /* force reset */
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/* handle the reset */
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imx_timerg_reset(DEVICE(s));
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imx_gpt_reset(DEVICE(s));
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} else {
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/* set our freq, as the source might have changed */
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imx_timerg_set_freq(s);
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imx_gpt_set_freq(s);
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if ((oldreg ^ s->cr) & GPT_CR_EN) {
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if (s->cr & GPT_CR_EN) {
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if (s->cr & GPT_CR_ENMOD) {
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s->next_timeout = TIMER_MAX;
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ptimer_set_count(s->timer, TIMER_MAX);
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imx_timerg_compute_next_timeout(s, false);
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imx_gpt_compute_next_timeout(s, false);
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}
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ptimer_run(s->timer, 1);
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} else {
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@ -429,19 +430,19 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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case 1: /* Prescaler */
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s->pr = value & 0xfff;
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imx_timerg_set_freq(s);
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imx_gpt_set_freq(s);
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break;
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case 2: /* SR */
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s->sr &= ~(value & 0x3f);
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imx_timerg_update(s);
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imx_gpt_update_int(s);
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break;
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case 3: /* IR -- interrupt register */
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s->ir = value & 0x3f;
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imx_timerg_update(s);
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imx_gpt_update_int(s);
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imx_timerg_compute_next_timeout(s, false);
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imx_gpt_compute_next_timeout(s, false);
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break;
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@ -455,7 +456,7 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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}
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/* compute the new timeout */
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imx_timerg_compute_next_timeout(s, false);
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imx_gpt_compute_next_timeout(s, false);
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break;
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@ -463,7 +464,7 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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s->ocr2 = value;
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/* compute the new timeout */
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imx_timerg_compute_next_timeout(s, false);
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imx_gpt_compute_next_timeout(s, false);
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break;
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@ -471,7 +472,7 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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s->ocr3 = value;
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/* compute the new timeout */
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imx_timerg_compute_next_timeout(s, false);
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imx_gpt_compute_next_timeout(s, false);
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break;
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@ -481,80 +482,76 @@ static void imx_timerg_write(void *opaque, hwaddr offset,
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}
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}
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static void imx_timerg_timeout(void *opaque)
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static void imx_gpt_timeout(void *opaque)
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{
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IMXTimerGState *s = (IMXTimerGState *)opaque;
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IMXGPTState *s = IMX_GPT(opaque);
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DPRINTF("\n");
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s->sr |= s->next_int;
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s->next_int = 0;
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imx_timerg_compute_next_timeout(s, true);
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imx_gpt_compute_next_timeout(s, true);
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imx_timerg_update(s);
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imx_gpt_update_int(s);
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if (s->freq && (s->cr & GPT_CR_EN)) {
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ptimer_run(s->timer, 1);
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}
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}
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static const MemoryRegionOps imx_timerg_ops = {
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.read = imx_timerg_read,
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.write = imx_timerg_write,
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static const MemoryRegionOps imx_gpt_ops = {
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.read = imx_gpt_read,
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.write = imx_gpt_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int imx_timerg_init(SysBusDevice *dev)
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static void imx_gpt_realize(DeviceState *dev, Error **errp)
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{
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IMXTimerGState *s = FROM_SYSBUS(IMXTimerGState, dev);
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IMXGPTState *s = IMX_GPT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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QEMUBH *bh;
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->iomem, &imx_timerg_ops,
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s, TYPE_IMX_GPT,
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, &imx_gpt_ops, s, TYPE_IMX_GPT,
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0x00001000);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_mmio(sbd, &s->iomem);
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bh = qemu_bh_new(imx_timerg_timeout, s);
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bh = qemu_bh_new(imx_gpt_timeout, s);
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s->timer = ptimer_init(bh);
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/* Hard reset resets extra bits in CR */
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s->cr = 0;
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return 0;
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}
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void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
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{
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IMXTimerGState *pp;
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IMXGPTState *pp;
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DeviceState *dev;
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dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq);
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pp = container_of(dev, IMXTimerGState, busdev.qdev);
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pp = IMX_GPT(dev);
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pp->ccm = ccm;
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}
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static void imx_timerg_class_init(ObjectClass *klass, void *data)
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static void imx_gpt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = imx_timerg_init;
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dc->vmsd = &vmstate_imx_timerg;
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dc->reset = imx_timerg_reset;
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_gpt_realize;
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dc->reset = imx_gpt_reset;
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dc->vmsd = &vmstate_imx_timer_gpt;
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dc->desc = "i.MX general timer";
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}
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static const TypeInfo imx_timerg_info = {
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static const TypeInfo imx_gpt_info = {
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.name = TYPE_IMX_GPT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXTimerGState),
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.class_init = imx_timerg_class_init,
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.instance_size = sizeof(IMXGPTState),
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.class_init = imx_gpt_class_init,
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};
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static void imx_timer_register_types(void)
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static void imx_gpt_register_types(void)
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{
|
||||
type_register_static(&imx_timerg_info);
|
||||
type_register_static(&imx_gpt_info);
|
||||
}
|
||||
|
||||
type_init(imx_timer_register_types)
|
||||
type_init(imx_gpt_register_types)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user