From 66b5ad561552c5c77058502ea3c7f04316937b64 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 28 Jan 2022 13:15:04 +0100 Subject: [PATCH] target/ppc: 405: Alignment exception cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no DSISR in the 405. It uses DEAR which we already set earlier at ppc_cpu_do_unaligned_access. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1f915f607d..55f6b0e981 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -474,13 +474,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_EXTERNAL: /* External input */ break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) {