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QOM patches for 2020-06-15

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Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-06-15' into staging

QOM patches for 2020-06-15

# gpg: Signature made Mon 15 Jun 2020 21:07:19 BST
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-qom-2020-06-15: (84 commits)
  MAINTAINERS: Make section QOM cover hw/core/*bus.c as well
  qdev: qdev_init_nofail() is now unused, drop
  qdev: Convert bus-less devices to qdev_realize() with Coccinelle
  qdev: Use qdev_realize() in qdev_device_add()
  qdev: Make qdev_realize() support bus-less devices
  s390x/event-facility: Simplify creation of SCLP event devices
  microbit: Eliminate two local variables in microbit_init()
  sysbus: sysbus_init_child_obj() is now unused, drop
  sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 4
  sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3
  sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
  sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
  qdev: Drop qdev_realize() support for null bus
  sysbus: Convert to sysbus_realize() etc. with Coccinelle
  sysbus: New sysbus_realize(), sysbus_realize_and_unref()
  sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 2
  hw/arm/armsse: Pass correct child size to sysbus_init_child_obj()
  sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 1
  microbit: Tidy up sysbus_init_child_obj() @child argument
  sysbus: Drop useless OBJECT() in sysbus_init_child_obj() calls
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-06-16 11:48:22 +01:00
commit 6675a653d2
296 changed files with 2127 additions and 2452 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -1218,7 +1218,9 @@ S: Maintained
F: hw/ppc/pnv*
F: hw/intc/pnv*
F: hw/intc/xics_pnv.c
F: hw/pci-host/pnv*
F: include/hw/ppc/pnv*
F: include/hw/pci-host/pnv*
F: pc-bios/skiboot.lid
F: tests/qtest/pnv*
@ -2298,6 +2300,8 @@ R: Eduardo Habkost <ehabkost@redhat.com>
S: Supported
F: docs/qdev-device-use.txt
F: hw/core/qdev*
F: hw/core/bus.c
F: hw/core/sysbus.c
F: include/hw/qdev*
F: include/monitor/qdev.h
F: include/qom/

2
hw/acpi/pcihp.c
View File

@ -266,7 +266,7 @@ void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
{
trace_acpi_pci_unplug(PCI_SLOT(PCI_DEVICE(dev)->devfn),
acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev))));
object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
qdev_unrealize(dev);
}
void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,

6
hw/acpi/piix4.c
View File

@ -514,10 +514,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm)
{
PCIDevice *pci_dev;
DeviceState *dev;
PIIX4PMState *s;
dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
if (piix4_pm) {
*piix4_pm = dev;
@ -531,7 +533,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
s->use_acpi_pci_hotplug = false;
}
qdev_init_nofail(dev);
pci_realize_and_unref(pci_dev, bus, &error_fatal);
return s->smb.smbus;
}

4
hw/alpha/typhoon.c
View File

@ -826,7 +826,7 @@ PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq,
PCIBus *b;
int i;
dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
dev = qdev_new(TYPE_TYPHOON_PCI_HOST_BRIDGE);
s = TYPHOON_PCI_HOST_BRIDGE(dev);
phb = PCI_HOST_BRIDGE(dev);
@ -889,7 +889,7 @@ PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq,
&s->pchip.reg_mem, &s->pchip.reg_io,
0, 64, TYPE_PCI_BUS);
phb->bus = b;
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Host memory as seen from the PCI side, via the IOMMU. */
memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),

50
hw/arm/allwinner-a10.c
View File

@ -41,37 +41,31 @@ static void aw_a10_init(Object *obj)
{
AwA10State *s = AW_A10(obj);
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
ARM_CPU_TYPE_NAME("cortex-a8"),
&error_abort, NULL);
object_initialize_child(obj, "cpu", &s->cpu,
ARM_CPU_TYPE_NAME("cortex-a8"));
sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
TYPE_AW_A10_PIC);
object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
TYPE_AW_A10_PIT);
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
TYPE_ALLWINNER_AHCI);
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
if (machine_usb(current_machine)) {
int i;
for (i = 0; i < AW_A10_NUM_USB; i++) {
sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]),
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ohci[*]", &s->ohci[i],
TYPE_SYSBUS_OHCI);
}
}
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN4I);
object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
TYPE_AW_RTC_SUN4I);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
@ -80,13 +74,13 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
SysBusDevice *sysbusdev;
Error *err = NULL;
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->intc), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -99,7 +93,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -123,7 +117,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -132,7 +126,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
if (err) {
error_propagate(errp, err);
return;
@ -155,8 +149,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->ehci[i]), true,
"companion-enable", &error_fatal);
object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
AW_A10_EHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
@ -164,8 +157,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus",
&error_fatal);
object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
AW_A10_OHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
@ -174,14 +166,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
}
/* SD/MMC */
qdev_init_nofail(DEVICE(&s->mmc0));
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus");
/* RTC */
qdev_init_nofail(DEVICE(&s->rtc));
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
}

57
hw/arm/allwinner-h3.c
View File

@ -194,50 +194,39 @@ static void allwinner_h3_init(Object *obj)
s->memmap = allwinner_h3_memmap;
for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
ARM_CPU_TYPE_NAME("cortex-a7"),
&error_abort, NULL);
object_initialize_child(obj, "cpu[*]", &s->cpus[i],
ARM_CPU_TYPE_NAME("cortex-a7"));
}
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
TYPE_ARM_GIC);
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
TYPE_AW_A10_PIT);
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
"clk0-freq");
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq");
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
TYPE_AW_H3_CCU);
object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
TYPE_AW_H3_SYSCTRL);
object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
TYPE_AW_CPUCFG);
object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
TYPE_AW_SID);
object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
"identifier");
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN5I);
object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
TYPE_AW_SUN8I_EMAC);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
TYPE_AW_H3_DRAMC);
object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
"ram-addr");
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
"ram-size");
sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
TYPE_AW_RTC_SUN6I);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@ -261,7 +250,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
/* Mark realized */
qdev_init_nofail(DEVICE(&s->cpus[i]));
qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
}
/* Generic Interrupt Controller */
@ -271,7 +260,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
qdev_init_nofail(DEVICE(&s->gic));
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
@ -322,7 +311,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
}
/* Timer */
qdev_init_nofail(DEVICE(&s->timer));
sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
@ -344,23 +333,23 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
&s->sram_c);
/* Clock Control Unit */
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
/* System Control */
qdev_init_nofail(DEVICE(&s->sysctrl));
sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
/* CPU Configuration */
qdev_init_nofail(DEVICE(&s->cpucfg));
sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
/* Security Identifier */
qdev_init_nofail(DEVICE(&s->sid));
sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
/* SD/MMC */
qdev_init_nofail(DEVICE(&s->mmc0));
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
@ -373,7 +362,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
qdev_init_nofail(DEVICE(&s->emac));
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
@ -423,13 +412,13 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
/* DRAMC */
qdev_init_nofail(DEVICE(&s->dramc));
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
/* RTC */
qdev_init_nofail(DEVICE(&s->rtc));
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
/* Unimplemented devices */

174
hw/arm/armsse.c
View File

@ -251,15 +251,13 @@ static void armsse_init(Object *obj)
char *name;
name = g_strdup_printf("cluster%d", i);
object_initialize_child(obj, name, &s->cluster[i],
sizeof(s->cluster[i]), TYPE_CPU_CLUSTER,
&error_abort, NULL);
object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i);
g_free(name);
name = g_strdup_printf("armv7m%d", i);
sysbus_init_child_obj(OBJECT(&s->cluster[i]), name,
&s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M);
object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
TYPE_ARMV7M);
qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m33"));
g_free(name);
@ -274,74 +272,61 @@ static void armsse_init(Object *obj)
}
}
sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl),
TYPE_IOTKIT_SECCTL);
sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0),
TYPE_TZ_PPC);
sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1),
TYPE_TZ_PPC);
object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL);
object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC);
object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC);
for (i = 0; i < info->sram_banks; i++) {
char *name = g_strdup_printf("mpc%d", i);
sysbus_init_child_obj(obj, name, &s->mpc[i],
sizeof(s->mpc[i]), TYPE_TZ_MPC);
object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC);
g_free(name);
}
object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate,
sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
TYPE_OR_IRQ);
for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
SplitIRQ *splitter = &s->mpc_irq_splitter[i];
object_initialize_child(obj, name, splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_abort, NULL);
object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0),
TYPE_CMSDK_APB_TIMER);
sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1),
TYPE_CMSDK_APB_TIMER);
sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer),
TYPE_CMSDK_APB_TIMER);
sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer),
TYPE_CMSDK_APB_DUALTIMER);
sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog,
sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG);
sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog,
sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG);
sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog,
sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG);
sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl,
sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL);
sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo,
sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER);
object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER);
object_initialize_child(obj, "s32ktimer", &s->s32ktimer,
TYPE_CMSDK_APB_TIMER);
object_initialize_child(obj, "dualtimer", &s->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog,
TYPE_CMSDK_APB_WATCHDOG);
object_initialize_child(obj, "nswatchdog", &s->nswatchdog,
TYPE_CMSDK_APB_WATCHDOG);
object_initialize_child(obj, "swatchdog", &s->swatchdog,
TYPE_CMSDK_APB_WATCHDOG);
object_initialize_child(obj, "armsse-sysctl", &s->sysctl,
TYPE_IOTKIT_SYSCTL);
object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo,
TYPE_IOTKIT_SYSINFO);
if (info->has_mhus) {
sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
TYPE_ARMSSE_MHU);
sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
TYPE_ARMSSE_MHU);
object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU);
object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU);
}
if (info->has_ppus) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("CPU%dCORE_PPU", i);
int ppuidx = CPU0CORE_PPU + i;
sysbus_init_child_obj(obj, name, &s->ppu[ppuidx],
sizeof(s->ppu[ppuidx]),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, name, &s->ppu[ppuidx],
TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU],
sizeof(s->ppu[DBG_PPU]),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU],
TYPE_UNIMPLEMENTED_DEVICE);
for (i = 0; i < info->sram_banks; i++) {
char *name = g_strdup_printf("RAM%d_PPU", i);
int ppuidx = RAM0_PPU + i;
sysbus_init_child_obj(obj, name, &s->ppu[ppuidx],
sizeof(s->ppu[ppuidx]),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, name, &s->ppu[ppuidx],
TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
@ -349,9 +334,8 @@ static void armsse_init(Object *obj)
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cachectrl%d", i);
sysbus_init_child_obj(obj, name, &s->cachectrl[i],
sizeof(s->cachectrl[i]),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, name, &s->cachectrl[i],
TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
@ -359,9 +343,8 @@ static void armsse_init(Object *obj)
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpusecctrl%d", i);
sysbus_init_child_obj(obj, name, &s->cpusecctrl[i],
sizeof(s->cpusecctrl[i]),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, name, &s->cpusecctrl[i],
TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
@ -369,27 +352,21 @@ static void armsse_init(Object *obj)
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpuid%d", i);
sysbus_init_child_obj(obj, name, &s->cpuid[i],
sizeof(s->cpuid[i]),
TYPE_ARMSSE_CPUID);
object_initialize_child(obj, name, &s->cpuid[i],
TYPE_ARMSSE_CPUID);
g_free(name);
}
}
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
sizeof(s->nmi_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ);
object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate,
sizeof(s->ppc_irq_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
TYPE_OR_IRQ);
object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter,
sizeof(s->sec_resp_splitter), TYPE_SPLIT_IRQ,
&error_abort, NULL);
TYPE_SPLIT_IRQ);
for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
char *name = g_strdup_printf("ppc-irq-splitter-%d", i);
SplitIRQ *splitter = &s->ppc_irq_splitter[i];
object_initialize_child(obj, name, splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_abort, NULL);
object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
if (info->num_cpus > 1) {
@ -398,8 +375,7 @@ static void armsse_init(Object *obj)
char *name = g_strdup_printf("cpu-irq-splitter%d", i);
SplitIRQ *splitter = &s->cpu_irq_splitter[i];
object_initialize_child(obj, name, splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_abort, NULL);
object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
}
@ -446,7 +422,7 @@ static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr)
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", 0x1000);
qdev_init_nofail(dev);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr);
}
@ -597,7 +573,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(cpuobj, true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(cpuobj), &err);
if (err) {
error_propagate(errp, err);
return;
@ -608,8 +584,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* CPU must exist and have been parented into the cluster before
* the cluster is realized.
*/
object_property_set_bool(OBJECT(&s->cluster[i]),
true, "realized", &err);
qdev_realize(DEVICE(&s->cluster[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -645,7 +620,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(splitter, true, "realized", &err);
qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -678,7 +653,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
/* Security controller */
object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->secctl), &err);
if (err) {
error_propagate(errp, err);
return;
@ -701,8 +676,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->sec_resp_splitter), true,
"realized", &err);
qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -730,7 +704,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -753,8 +727,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true,
"realized", &err);
qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -773,7 +746,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* map its upstream ends to the right place in the container.
*/
qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer0), &err);
if (err) {
error_propagate(errp, err);
return;
@ -788,7 +761,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer1), &err);
if (err) {
error_propagate(errp, err);
return;
@ -804,7 +777,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), &err);
if (err) {
error_propagate(errp, err);
return;
@ -833,8 +806,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
int cpunum;
SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
object_property_set_bool(OBJECT(&s->mhu[i]), true,
"realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -865,7 +837,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
}
object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), &err);
if (err) {
error_propagate(errp, err);
return;
@ -914,8 +886,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true,
"realized", &err);
qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -938,8 +909,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
object_property_set_bool(OBJECT(&s->cachectrl[i]), true,
"realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -957,8 +927,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true,
"realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -973,8 +942,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
MemoryRegion *mr;
qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
object_property_set_bool(OBJECT(&s->cpuid[i]), true,
"realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -990,7 +958,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* 0x4002f000: S32K timer
*/
qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1004,7 +972,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1042,7 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1058,7 +1026,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
"INITSVTOR0_RST", &err);
object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
"INITSVTOR1_RST", &err);
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1093,7 +1061,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err);
qdev_realize(DEVICE(&s->nmi_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -1102,7 +1070,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1114,7 +1082,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1124,7 +1092,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
@ -1141,7 +1109,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(splitter, true, "realized", &err);
qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -1188,7 +1156,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(splitter), true, "realized", &err);
qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;

18
hw/arm/armv7m.c
View File

@ -136,13 +136,13 @@ static void armv7m_instance_init(Object *obj)
memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC);
object_property_add_alias(obj, "num-irq",
OBJECT(&s->nvic), "num-irq");
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
sizeof(s->bitband[i]), TYPE_BITBAND);
object_initialize_child(obj, "bitband[*]", &s->bitband[i],
TYPE_BITBAND);
}
}
@ -216,14 +216,14 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
s->cpu->env.nvic = &s->nvic;
s->nvic.cpu = s->cpu;
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
qdev_realize(DEVICE(s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
/* Note that we must realize the NVIC after the CPU */
object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->nvic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -245,8 +245,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0xe000e000,
sysbus_mmio_get_region(sbd, 0));
if (s->enable_bitband) {
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
if (s->enable_bitband) {
Object *obj = OBJECT(&s->bitband[i]);
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
@ -257,7 +257,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
object_property_set_link(obj, OBJECT(s->board_memory),
"source-memory", &error_abort);
object_property_set_bool(obj, true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(obj), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -265,6 +265,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, bitband_output_addr[i],
sysbus_mmio_get_region(sbd, 0));
} else {
object_unparent(OBJECT(&s->bitband[i]));
}
}
}

60
hw/arm/aspeed.c
View File

@ -225,12 +225,12 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
fl->flash = qdev_new(flashtype);
if (dinfo) {
qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
errp);
}
qdev_init_nofail(fl->flash);
qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
@ -241,13 +241,14 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
{
DeviceState *card;
card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
TYPE_SD_CARD);
card = qdev_new(TYPE_SD_CARD);
if (dinfo) {
qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
qdev_realize_and_unref(card,
qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
&error_fatal);
}
static void aspeed_machine_init(MachineState *machine)
@ -258,6 +259,7 @@ static void aspeed_machine_init(MachineState *machine)
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
ram_addr_t max_ram_size;
int i;
NICInfo *nd = &nd_table[0];
bmc = g_new0(AspeedBoardState, 1);
@ -265,9 +267,7 @@ static void aspeed_machine_init(MachineState *machine)
4 * GiB);
memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
(sizeof(bmc->soc)), amc->soc_name, &error_abort,
NULL);
object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
@ -277,14 +277,20 @@ static void aspeed_machine_init(MachineState *machine)
object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
&error_fatal);
for (i = 0; i < sc->macs_num; i++) {
if ((amc->macs_mask & (1 << i)) && nd->used) {
qemu_check_nic_model(nd, TYPE_FTGMAC100);
qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
nd++;
}
}
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
&error_abort);
object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container),
"dram", &error_abort);
if (machine->kernel_filename) {
@ -296,8 +302,7 @@ static void aspeed_machine_init(MachineState *machine)
object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
"hw-prot-key", &error_abort);
}
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SDRAM],
@ -337,7 +342,7 @@ static void aspeed_machine_init(MachineState *machine)
}
}
if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
if (machine->kernel_filename && sc->num_cpus > 1) {
/* With no u-boot we must set up a boot stub for the secondary CPU */
MemoryRegion *smpboot = g_new(MemoryRegion, 1);
memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
@ -352,7 +357,7 @@ static void aspeed_machine_init(MachineState *machine)
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
aspeed_board_binfo.nb_cpus = sc->num_cpus;
if (amc->i2c_init) {
amc->i2c_init(bmc);
@ -549,16 +554,23 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
"boot directly from CE0 flash device");
}
static int aspeed_soc_num_cpus(const char *soc_name)
{
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
return sc->num_cpus;
}
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->init = aspeed_machine_init;
mc->max_cpus = ASPEED_CPUS_NUM;
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_parallel = 1;
mc->default_ram_id = "ram";
amc->macs_mask = ASPEED_MAC0_ON;
aspeed_machine_class_props_init(oc);
}
@ -576,6 +588,8 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 256 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
@ -591,6 +605,8 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = ast2500_evb_i2c_init;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
@ -606,6 +622,8 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = romulus_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
@ -621,6 +639,8 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = sonorapass_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
@ -636,6 +656,8 @@ static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = swift_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
@ -651,6 +673,8 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = witherspoon_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
@ -665,8 +689,11 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
amc->fmc_model = "w25q512jv";
amc->spi_model = "mx66u51235f";
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = ast2600_evb_i2c_init;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
@ -681,8 +708,11 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
amc->fmc_model = "mx66l1g45g";
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
};
static const TypeInfo aspeed_machine_types[] = {

133
hw/arm/aspeed_ast2600.c
View File

@ -127,14 +127,11 @@ static void aspeed_soc_ast2600_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
sizeof(s->cpu[i]), sc->cpu_type,
&error_abort, NULL);
object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
typename);
object_initialize_child(obj, "scu", &s->scu, typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
@ -144,39 +141,33 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
TYPE_A15MPCORE_PRIV);
sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
TYPE_ASPEED_RTC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
sizeof(s->timerctrl), typename);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
typename);
object_initialize_child(obj, "i2c", &s->i2c, typename);
snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
typename);
object_initialize_child(obj, "fmc", &s->fmc, typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
sizeof(s->spi[i]), typename);
object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
}
for (i = 0; i < sc->ehcis_num; i++) {
sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
}
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
typename);
object_initialize_child(obj, "sdmc", &s->sdmc, typename);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size");
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
@ -184,49 +175,42 @@ static void aspeed_soc_ast2600_init(Object *obj)
for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
sizeof(s->wdt[i]), typename);
object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
}
for (i = 0; i < sc->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
TYPE_FTGMAC100);
sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
TYPE_ASPEED_MII);
object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
}
sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
TYPE_ASPEED_XDMA);
object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
typename);
object_initialize_child(obj, "gpio", &s->gpio, typename);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
sizeof(s->gpio_1_8v), typename);
object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
OBJECT(&s->sdhci.slots[i]),
sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
object_initialize_child(obj, "sd-controller.sdhci[*]",
&s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
}
sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
sizeof(s->emmc), TYPE_ASPEED_SDHCI);
object_initialize_child(obj, "emmc-controller", &s->emmc,
TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
sysbus_init_child_obj(obj, "emmc-controller.sdhci",
OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
TYPE_SYSBUS_SDHCI);
object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
TYPE_SYSBUS_SDHCI);
}
/*
@ -255,17 +239,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
0x1000);
if (s->num_cpus > sc->num_cpus) {
warn_report("%s: invalid number of CPUs %d, using default %d",
sc->name, s->num_cpus, sc->num_cpus);
s->num_cpus = sc->num_cpus;
}
/* CPU */
for (i = 0; i < s->num_cpus; i++) {
for (i = 0; i < sc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
if (s->num_cpus > 1) {
if (sc->num_cpus > 1) {
object_property_set_int(OBJECT(&s->cpu[i]),
ASPEED_A7MPCORE_ADDR,
"reset-cbar", &error_abort);
@ -281,7 +259,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
* is needed when using -kernel
*/
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -289,28 +267,27 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
/* A7MPCORE */
object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu",
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore),
ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
for (i = 0; i < s->num_cpus; i++) {
for (i = 0; i < sc->num_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
DeviceState *d = DEVICE(qemu_get_cpu(i));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
sysbus_connect_irq(sbd, i + s->num_cpus, irq);
sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
}
/* SRAM */
@ -324,7 +301,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_SRAM], &s->sram);
/* SCU */
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err) {
error_propagate(errp, err);
return;
@ -332,7 +309,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
/* RTC */
object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -344,7 +321,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl),
OBJECT(&s->scu), "scu", &error_abort);
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err);
if (err) {
error_propagate(errp, err);
return;
@ -369,7 +346,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err);
if (err) {
error_propagate(errp, err);
return;
@ -397,7 +374,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -417,8 +394,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&local_err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
@ -432,7 +408,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* EHCI */
for (i = 0; i < sc->ehcis_num; i++) {
object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -444,7 +420,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -457,7 +433,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->wdt[i]),
OBJECT(&s->scu), "scu", &error_abort);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -467,12 +443,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
/* Net */
for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
&local_err);
sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
@ -485,8 +459,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
"nic", &error_abort);
object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
&err);
sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -497,7 +470,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
/* XDMA */
object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err);
if (err) {
error_propagate(errp, err);
return;
@ -508,7 +481,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_XDMA));
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
@ -517,7 +490,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO));
object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err);
if (err) {
error_propagate(errp, err);
return;
@ -528,7 +501,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
/* SDHCI */
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
@ -539,7 +512,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_SDHCI));
/* eMMC */
object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err);
if (err) {
error_propagate(errp, err);
return;

96
hw/arm/aspeed_soc.c
View File

@ -142,14 +142,11 @@ static void aspeed_soc_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
sizeof(s->cpu[i]), sc->cpu_type,
&error_abort, NULL);
object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
typename);
object_initialize_child(obj, "scu", &s->scu, typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
@ -159,39 +156,32 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
TYPE_ASPEED_VIC);
object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
TYPE_ASPEED_RTC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
sizeof(s->timerctrl), typename);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
typename);
object_initialize_child(obj, "i2c", &s->i2c, typename);
snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
typename);
object_initialize_child(obj, "fmc", &s->fmc, typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
sizeof(s->spi[i]), typename);
object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
}
for (i = 0; i < sc->ehcis_num; i++) {
sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
}
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
typename);
object_initialize_child(obj, "sdmc", &s->sdmc, typename);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size");
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
@ -199,31 +189,27 @@ static void aspeed_soc_init(Object *obj)
for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
sizeof(s->wdt[i]), typename);
object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
}
for (i = 0; i < sc->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
TYPE_FTGMAC100);
}
sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
TYPE_ASPEED_XDMA);
object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
typename);
object_initialize_child(obj, "gpio", &s->gpio, typename);
sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
TYPE_ASPEED_SDHCI);
object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
TYPE_SYSBUS_SDHCI);
}
}
@ -242,15 +228,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
0x1000);
if (s->num_cpus > sc->num_cpus) {
warn_report("%s: invalid number of CPUs %d, using default %d",
sc->name, s->num_cpus, sc->num_cpus);
s->num_cpus = sc->num_cpus;
}
/* CPU */
for (i = 0; i < s->num_cpus; i++) {
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
for (i = 0; i < sc->num_cpus; i++) {
qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -268,7 +248,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_SRAM], &s->sram);
/* SCU */
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err) {
error_propagate(errp, err);
return;
@ -276,7 +256,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
/* VIC */
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->vic), &err);
if (err) {
error_propagate(errp, err);
return;
@ -288,7 +268,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
/* RTC */
object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -300,7 +280,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl),
OBJECT(&s->scu), "scu", &error_abort);
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err);
if (err) {
error_propagate(errp, err);
return;
@ -325,7 +305,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err);
if (err) {
error_propagate(errp, err);
return;
@ -346,7 +326,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -360,8 +340,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&local_err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
@ -375,7 +354,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* EHCI */
for (i = 0; i < sc->ehcis_num; i++) {
object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -387,7 +366,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -400,7 +379,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->wdt[i]),
OBJECT(&s->scu), "scu", &error_abort);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -410,12 +389,10 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
/* Net */
for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
&local_err);
sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
@ -428,7 +405,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
/* XDMA */
object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err);
if (err) {
error_propagate(errp, err);
return;
@ -439,7 +416,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_XDMA));
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
@ -449,7 +426,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_GPIO));
/* SDHCI */
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
@ -460,7 +437,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_SDHCI));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),

81
hw/arm/bcm2835_peripherals.c
View File

@ -27,12 +27,10 @@ static void create_unimp(BCM2835PeripheralState *ps,
UnimplementedDeviceState *uds,
const char *name, hwaddr ofs, hwaddr size)
{
sysbus_init_child_obj(OBJECT(ps), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
memory_region_add_subregion_overlap(&ps->peri_mr, ofs,
sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000);
}
@ -55,37 +53,34 @@ static void bcm2835_peripherals_init(Object *obj)
MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT);
/* Interrupt Controller */
sysbus_init_child_obj(obj, "ic", &s->ic, sizeof(s->ic), TYPE_BCM2835_IC);
object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC);
/* SYS Timer */
sysbus_init_child_obj(obj, "systimer", &s->systmr, sizeof(s->systmr),
TYPE_BCM2835_SYSTIMER);
object_initialize_child(obj, "systimer", &s->systmr,
TYPE_BCM2835_SYSTIMER);
/* UART0 */
sysbus_init_child_obj(obj, "uart0", &s->uart0, sizeof(s->uart0),
TYPE_PL011);
object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011);
/* AUX / UART1 */
sysbus_init_child_obj(obj, "aux", &s->aux, sizeof(s->aux),
TYPE_BCM2835_AUX);
object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX);
/* Mailboxes */
sysbus_init_child_obj(obj, "mbox", &s->mboxes, sizeof(s->mboxes),
TYPE_BCM2835_MBOX);
object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX);
object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr",
OBJECT(&s->mbox_mr));
/* Framebuffer */
sysbus_init_child_obj(obj, "fb", &s->fb, sizeof(s->fb), TYPE_BCM2835_FB);
object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB);
object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size");
object_property_add_const_link(OBJECT(&s->fb), "dma-mr",
OBJECT(&s->gpu_bus_mr));
/* Property channel */
sysbus_init_child_obj(obj, "property", &s->property, sizeof(s->property),
TYPE_BCM2835_PROPERTY);
object_initialize_child(obj, "property", &s->property,
TYPE_BCM2835_PROPERTY);
object_property_add_alias(obj, "board-rev", OBJECT(&s->property),
"board-rev");
@ -95,31 +90,25 @@ static void bcm2835_peripherals_init(Object *obj)
OBJECT(&s->gpu_bus_mr));
/* Random Number Generator */
sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
TYPE_BCM2835_RNG);
object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG);
/* Extended Mass Media Controller */
sysbus_init_child_obj(obj, "sdhci", &s->sdhci, sizeof(s->sdhci),
TYPE_SYSBUS_SDHCI);
object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI);
/* SDHOST */
sysbus_init_child_obj(obj, "sdhost", &s->sdhost, sizeof(s->sdhost),
TYPE_BCM2835_SDHOST);
object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST);
/* DMA Channels */
sysbus_init_child_obj(obj, "dma", &s->dma, sizeof(s->dma),
TYPE_BCM2835_DMA);
object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA);
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr));
/* Thermal */
sysbus_init_child_obj(obj, "thermal", &s->thermal, sizeof(s->thermal),
TYPE_BCM2835_THERMAL);
object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL);
/* GPIO */
sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
TYPE_BCM2835_GPIO);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO);
object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
OBJECT(&s->sdhci.sdbus));
@ -127,12 +116,10 @@ static void bcm2835_peripherals_init(Object *obj)
OBJECT(&s->sdhost.sdbus));
/* Mphi */
sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
TYPE_BCM2835_MPHI);
object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI);
/* DWC2 */
sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),
TYPE_DWC2_USB);
object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
OBJECT(&s->gpu_bus_mr));
@ -174,7 +161,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
}
/* Interrupt Controller */
object_property_set_bool(OBJECT(&s->ic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ic), &err);
if (err) {
error_propagate(errp, err);
return;
@ -185,7 +172,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
/* Sys Timer */
object_property_set_bool(OBJECT(&s->systmr), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->systmr), &err);
if (err) {
error_propagate(errp, err);
return;
@ -198,7 +185,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
/* UART0 */
qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
object_property_set_bool(OBJECT(&s->uart0), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart0), &err);
if (err) {
error_propagate(errp, err);
return;
@ -213,7 +200,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
/* AUX / UART1 */
qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1));
object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->aux), &err);
if (err) {
error_propagate(errp, err);
return;
@ -226,7 +213,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
INTERRUPT_AUX));
/* Mailboxes */
object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), &err);
if (err) {
error_propagate(errp, err);
return;
@ -252,7 +239,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->fb), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->fb), &err);
if (err) {
error_propagate(errp, err);
return;
@ -264,7 +251,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
/* Property channel */
object_property_set_bool(OBJECT(&s->property), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->property), &err);
if (err) {
error_propagate(errp, err);
return;
@ -277,7 +264,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
/* Random Number Generator */
object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err);
if (err) {
error_propagate(errp, err);
return;
@ -306,7 +293,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
@ -319,7 +306,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
INTERRUPT_ARASANSDIO));
/* SDHOST */
object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), &err);
if (err) {
error_propagate(errp, err);
return;
@ -332,7 +319,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
INTERRUPT_SDIO));
/* DMA Channels */
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->dma), &err);
if (err) {
error_propagate(errp, err);
return;
@ -351,7 +338,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
}
/* THERMAL */
object_property_set_bool(OBJECT(&s->thermal), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->thermal), &err);
if (err) {
error_propagate(errp, err);
return;
@ -360,7 +347,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0));
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
@ -372,7 +359,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
/* Mphi */
object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mphi), &err);
if (err) {
error_propagate(errp, err);
return;
@ -385,7 +372,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
INTERRUPT_HOSTPORT));
/* DWC2 */
object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), &err);
if (err) {
error_propagate(errp, err);
return;

17
hw/arm/bcm2836.c
View File

@ -53,15 +53,13 @@ static void bcm2836_init(Object *obj)
for (n = 0; n < BCM283X_NCPUS; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
sizeof(s->cpu[n].core), info->cpu_type,
&error_abort, NULL);
info->cpu_type);
}
sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control),
TYPE_BCM2836_CONTROL);
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
sysbus_init_child_obj(obj, "peripherals", &s->peripherals,
sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS);
object_initialize_child(obj, "peripherals", &s->peripherals,
TYPE_BCM2835_PERIPHERALS);
object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
"board-rev");
object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
@ -88,7 +86,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), &err);
if (err) {
error_propagate(errp, err);
return;
@ -101,7 +99,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
info->peri_base, 1);
/* bcm2836 interrupt controller (and mailboxes, etc.) */
object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->control), &err);
if (err) {
error_propagate(errp, err);
return;
@ -135,8 +133,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->cpu[n].core), true,
"realized", &err);
qdev_realize(DEVICE(&s->cpu[n].core), NULL, &err);
if (err) {
error_propagate(errp, err);
return;

6
hw/arm/cubieboard.c
View File

@ -80,7 +80,7 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
object_property_set_bool(OBJECT(a10), true, "realized", &err);
qdev_realize(DEVICE(a10), NULL, &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize Allwinner A10: ");
exit(1);
@ -92,9 +92,9 @@ static void cubieboard_init(MachineState *machine)
bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
/* Plug in SD card */
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);

16
hw/arm/digic.c
View File

@ -36,21 +36,17 @@ static void digic_init(Object *obj)
DigicState *s = DIGIC(obj);
int i;
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
ARM_CPU_TYPE_NAME("arm946"),
&error_abort, NULL);
object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
#define DIGIC_TIMER_NAME_MLEN 11
char name[DIGIC_TIMER_NAME_MLEN];
snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
TYPE_DIGIC_TIMER);
object_initialize_child(obj, name, &s->timer[i], TYPE_DIGIC_TIMER);
}
sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
TYPE_DIGIC_UART);
object_initialize_child(obj, "uart", &s->uart, TYPE_DIGIC_UART);
}
static void digic_realize(DeviceState *dev, Error **errp)
@ -66,14 +62,14 @@ static void digic_realize(DeviceState *dev, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -84,7 +80,7 @@ static void digic_realize(DeviceState *dev, Error **errp)
}
qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

2
hw/arm/digic_boards.c
View File

@ -62,7 +62,7 @@ static void digic4_board_init(MachineState *machine, DigicBoard *board)
exit(EXIT_FAILURE);
}
object_property_set_bool(OBJECT(s), true, "realized", &err);
qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize DIGIC SoC: ");
exit(1);

48
hw/arm/exynos4210.c
View File

@ -173,7 +173,7 @@ static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
DeviceState *dev;
int i;
dev = qdev_create(NULL, "pl330");
dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_events", nevents);
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", nreq);
@ -184,13 +184,13 @@ static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
qdev_prop_set_uint8(dev, "rd_q_dep", 8);
qdev_prop_set_uint8(dev, "data_width", width);
qdev_prop_set_uint16(dev, "data_buffer_dep", width);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base);
object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines",
&error_abort);
object_property_set_bool(OBJECT(orgate), true, "realized", &error_abort);
qdev_realize(DEVICE(orgate), NULL, &error_abort);
for (i = 0; i < nevents + 1; i++) {
sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
@ -223,7 +223,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
"mp-affinity", &error_abort);
object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
"reset-cbar", &error_abort);
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
}
/*** IRQs ***/
@ -232,9 +232,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
/* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
dev = qdev_create(NULL, "exynos4210.irq_gate");
dev = qdev_new("exynos4210.irq_gate");
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Get IRQ Gate input in gate_irq */
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
@ -247,10 +247,10 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
}
/* Private memory region and Internal GIC */
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][0]);
@ -263,10 +263,10 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
dev = qdev_create(NULL, "exynos4210.gic");
dev = qdev_new("exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
@ -279,9 +279,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
}
/* Internal Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.combiner");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
}
@ -289,10 +289,10 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
/* External Interrupt Combiner */
dev = qdev_create(NULL, "exynos4210.combiner");
dev = qdev_new("exynos4210.combiner");
qdev_prop_set_uint32(dev, "external", 1);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
}
@ -353,9 +353,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
NULL);
/* Multi Core Timer */
dev = qdev_create(NULL, "exynos4210.mct");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.mct");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < 4; n++) {
/* Connect global timer interrupts to Combiner gpio_in */
sysbus_connect_irq(busdev, n,
@ -379,9 +379,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
}
dev = qdev_create(NULL, "exynos4210.i2c");
qdev_init_nofail(dev);
dev = qdev_new("exynos4210.i2c");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
@ -423,19 +423,20 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
* public datasheet which is very similar (implementing
* MMC Specification Version 4.0 being the only difference noted)
*/
dev = qdev_create(NULL, TYPE_S3C_SDHCI);
dev = qdev_new(TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
di = drive_get(IF_SD, 0, n);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
qdev_init_nofail(carddev);
qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
&error_fatal);
}
/*** Display controller (FIMD) ***/
@ -481,8 +482,7 @@ static void exynos4210_init(Object *obj)
char *name = g_strdup_printf("pl330-irq-orgate%d", i);
qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
object_initialize_child(obj, name, orgate, sizeof(*orgate),
TYPE_OR_IRQ, &error_abort, NULL);
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
g_free(name);
}
}

11
hw/arm/exynos4_boards.c
View File

@ -81,11 +81,11 @@ static void lan9215_init(uint32_t base, qemu_irq irq)
/* This should be a 9215 but the 9118 is close enough */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "lan9118");
dev = qdev_create(NULL, TYPE_LAN9118);
dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
@ -128,10 +128,9 @@ exynos4_boards_init_common(MachineState *machine,
exynos4_boards_init_ram(s, get_system_memory(),
exynos4_board_ram_size[board_type]);
sysbus_init_child_obj(OBJECT(machine), "soc",
&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_fatal);
object_initialize_child(OBJECT(machine), "soc", &s->soc,
TYPE_EXYNOS4210_SOC);
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
return s;
}

64
hw/arm/fsl-imx25.c
View File

@ -38,56 +38,45 @@ static void fsl_imx25_init(Object *obj)
FslIMX25State *s = FSL_IMX25(obj);
int i;
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
ARM_CPU_TYPE_NAME("arm926"),
&error_abort, NULL);
object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
TYPE_IMX_AVIC);
object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM);
for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
}
for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
TYPE_IMX25_GPT);
object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT);
}
for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
TYPE_IMX_EPIT);
object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
}
sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC);
sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
TYPE_IMX_RNGC);
object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC);
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
TYPE_IMX_USDHC);
object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC);
}
for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
TYPE_CHIPIDEA);
object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA);
}
sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
}
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
@ -96,13 +85,13 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
uint8_t i;
Error *err = NULL;
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
if (err) {
error_propagate(errp, err);
return;
@ -113,7 +102,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
@ -135,7 +124,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -160,7 +149,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
s->gpt[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -183,7 +172,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -196,7 +185,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->fec), &err);
if (err) {
error_propagate(errp, err);
return;
@ -205,7 +194,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rngc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -225,7 +214,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -248,7 +237,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
};
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -274,7 +263,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
"capareg", &err);
object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -295,8 +284,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{ FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
};
object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
qdev_get_gpio_in(DEVICE(&s->avic),
@ -306,7 +294,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
/* Watchdog */
object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
&error_abort);
object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
qdev_get_gpio_in(DEVICE(&s->avic),

43
hw/arm/fsl-imx31.c
View File

@ -33,38 +33,31 @@ static void fsl_imx31_init(Object *obj)
FslIMX31State *s = FSL_IMX31(obj);
int i;
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
ARM_CPU_TYPE_NAME("arm1136"),
&error_abort, NULL);
object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
TYPE_IMX_AVIC);
object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
}
sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
TYPE_IMX_EPIT);
object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
}
for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
}
sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
}
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
@ -73,13 +66,13 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
uint16_t i;
Error *err = NULL;
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
if (err) {
error_propagate(errp, err);
return;
@ -90,7 +83,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
@ -109,7 +102,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -123,7 +116,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
s->gpt.ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
if (err) {
error_propagate(errp, err);
return;
@ -145,7 +138,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -169,7 +162,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
};
/* Initialize the I2C */
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -195,7 +188,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -208,7 +201,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
}
/* Watchdog */
object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
/* On a real system, the first 16k is a `secure boot rom' */

76
hw/arm/fsl-imx6.c
View File

@ -43,74 +43,63 @@ static void fsl_imx6_init(Object *obj)
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
ARM_CPU_TYPE_NAME("cortex-a9"),
&error_abort, NULL);
object_initialize_child(obj, name, &s->cpu[i],
ARM_CPU_TYPE_NAME("cortex-a9"));
}
sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
TYPE_A9MPCORE_PRIV);
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i + 1);
sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
TYPE_IMX_EPIT);
object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
}
for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i + 1);
sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]),
TYPE_IMX_USDHC);
object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
}
for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
snprintf(name, NAME_SIZE, "usbphy%d", i);
sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
TYPE_IMX_USBPHY);
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
}
for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
TYPE_CHIPIDEA);
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
TYPE_IMX_SPI);
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
TYPE_IMX2_WDT);
object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET);
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@ -141,7 +130,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
"start-powered-off", &error_abort);
}
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
@ -155,7 +144,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
&error_abort);
object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err);
if (err) {
error_propagate(errp, err);
return;
@ -169,14 +158,14 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->src), &err);
if (err) {
error_propagate(errp, err);
return;
@ -198,7 +187,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -212,7 +201,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
s->gpt.ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
if (err) {
error_propagate(errp, err);
return;
@ -235,7 +224,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -258,7 +247,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -318,7 +307,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -350,7 +339,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
"capareg", &err);
object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -363,8 +352,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
/* USB */
for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
}
@ -376,8 +364,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
FSL_IMX6_USB_HOST3_IRQ,
};
object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
@ -399,7 +386,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
};
/* Initialize the SPI */
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -412,7 +399,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
}
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->eth), &err);
if (err) {
error_propagate(errp, err);
return;
@ -440,8 +427,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,

105
hw/arm/fsl-imx6ul.c
View File

@ -34,50 +34,46 @@ static void fsl_imx6ul_init(Object *obj)
char name[NAME_SIZE];
int i;
object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL);
object_initialize_child(obj, "cpu0", &s->cpu,
ARM_CPU_TYPE_NAME("cortex-a7"));
/*
* A7MPCORE
*/
sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
TYPE_A15MPCORE_PRIV);
object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
TYPE_A15MPCORE_PRIV);
/*
* CCM
*/
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
/*
* SRC
*/
sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
/*
* GPCv2
*/
sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
TYPE_IMX_GPCV2);
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
/*
* SNVS
*/
sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
TYPE_IMX7_SNVS);
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* GPR
*/
sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
TYPE_IMX7_GPR);
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
/*
* GPIOs 1 to 5
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
/*
@ -85,8 +81,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
TYPE_IMX7_GPT);
object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
}
/*
@ -94,8 +89,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
TYPE_IMX_EPIT);
object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
}
/*
@ -103,8 +97,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
TYPE_IMX_SPI);
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
/*
@ -112,8 +105,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
/*
@ -121,8 +113,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
/*
@ -130,20 +121,17 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
TYPE_IMX_ENET);
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
}
/* USB */
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
snprintf(name, NAME_SIZE, "usbphy%d", i);
sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
TYPE_IMX_USBPHY);
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
}
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
TYPE_CHIPIDEA);
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
/*
@ -151,8 +139,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
TYPE_IMX_USDHC);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
/*
@ -160,8 +147,7 @@ static void fsl_imx6ul_init(Object *obj)
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
TYPE_IMX2_WDT);
object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
}
@ -182,8 +168,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true,
"realized", &error_abort);
qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
/*
* A7MPCORE
@ -192,8 +177,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->a7mpcore),
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
sbd = SYS_BUS_DEVICE(&s->a7mpcore);
@ -225,8 +209,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
};
s->gpt[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
FSL_IMX6UL_GPTn_ADDR[i]);
@ -251,8 +234,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
};
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
FSL_IMX6UL_EPITn_ADDR[i]);
@ -290,8 +272,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_GPIO5_HIGH_IRQ,
};
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
FSL_IMX6UL_GPIOn_ADDR[i]);
@ -321,20 +302,19 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/*
* CCM
*/
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
/*
* SRC
*/
object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
/*
* GPCv2
*/
object_property_set_bool(OBJECT(&s->gpcv2), true,
"realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
/* Initialize all ECSPI */
@ -354,8 +334,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
};
/* Initialize the SPI */
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX6UL_SPIn_ADDR[i]);
@ -383,8 +362,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_I2C4_IRQ,
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
@ -420,8 +398,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
FSL_IMX6UL_UARTn_ADDR[i]);
@ -454,8 +431,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_ETH_NUM_TX_RINGS,
"tx-ring-num", &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
FSL_IMX6UL_ENETn_ADDR[i]);
@ -471,8 +447,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/* USB */
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
}
@ -482,8 +457,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_USB1_IRQ,
FSL_IMX6UL_USB2_IRQ,
};
object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
@ -505,8 +479,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_USDHC2_IRQ,
};
object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX6UL_USDHCn_ADDR[i]);
@ -519,7 +492,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/*
* SNVS
*/
object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
/*
@ -539,8 +512,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
FSL_IMX6UL_WDOGn_ADDR[i]);
@ -552,8 +524,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/*
* GPR
*/
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
/*

100
hw/arm/fsl-imx7.c
View File

@ -38,24 +38,22 @@ static void fsl_imx7_init(Object *obj)
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort,
NULL);
object_initialize_child(obj, name, &s->cpu[i],
ARM_CPU_TYPE_NAME("cortex-a7"));
}
/*
* A7MPCORE
*/
sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
TYPE_A15MPCORE_PRIV);
object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
TYPE_A15MPCORE_PRIV);
/*
* GPIOs 1 to 7
*/
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
/*
@ -63,38 +61,33 @@ static void fsl_imx7_init(Object *obj)
*/
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
TYPE_IMX7_GPT);
object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
}
/*
* CCM
*/
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
/*
* Analog
*/
sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog),
TYPE_IMX7_ANALOG);
object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
/*
* GPCv2
*/
sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
TYPE_IMX_GPCV2);
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
TYPE_IMX_SPI);
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
/*
@ -102,8 +95,7 @@ static void fsl_imx7_init(Object *obj)
*/
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
/*
@ -111,8 +103,7 @@ static void fsl_imx7_init(Object *obj)
*/
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
TYPE_IMX_ENET);
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
}
/*
@ -120,37 +111,32 @@ static void fsl_imx7_init(Object *obj)
*/
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
TYPE_IMX_USDHC);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
/*
* SNVS
*/
sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
TYPE_IMX7_SNVS);
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* Watchdog
*/
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
TYPE_IMX2_WDT);
object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
/*
* GPR
*/
sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie),
TYPE_DESIGNWARE_PCIE_HOST);
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
TYPE_CHIPIDEA);
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
}
@ -188,7 +174,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
"start-powered-off", &error_abort);
}
object_property_set_bool(o, true, "realized", &error_abort);
qdev_realize(DEVICE(o), NULL, &error_abort);
}
/*
@ -200,8 +186,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) {
@ -236,8 +221,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
};
s->gpt[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
}
@ -252,8 +236,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_GPIO7_ADDR,
};
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
}
@ -274,21 +257,19 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
/*
* CCM
*/
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
/*
* Analog
*/
object_property_set_bool(OBJECT(&s->analog), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
/*
* GPCv2
*/
object_property_set_bool(OBJECT(&s->gpcv2), true,
"realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
/* Initialize all ECSPI */
@ -308,8 +289,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
};
/* Initialize the SPI */
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX7_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
@ -332,8 +312,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_I2C4_IRQ,
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
@ -368,8 +347,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
@ -389,8 +367,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
"tx-ring-num", &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
@ -416,8 +393,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_USDHC3_IRQ,
};
object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX7_USDHCn_ADDR[i]);
@ -429,7 +405,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
/*
* SNVS
*/
object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
/*
@ -456,8 +432,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
@ -495,12 +470,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
FSL_IMX7_OCOTP_SIZE);
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
object_property_set_bool(OBJECT(&s->pcie), true,
"realized", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
@ -532,8 +505,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_USB3_IRQ,
};
object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX7_USBn_ADDR[i]);

28
hw/arm/highbank.c
View File

@ -280,7 +280,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
@ -311,21 +311,21 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
switch (machine_id) {
case CALXEDA_HIGHBANK:
dev = qdev_create(NULL, "l2x0");
qdev_init_nofail(dev);
dev = qdev_new("l2x0");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff12000);
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
break;
case CALXEDA_MIDWAY:
dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
dev = qdev_new(TYPE_A15MPCORE_PRIV);
break;
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
@ -338,18 +338,18 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = qdev_create(NULL, "sp804");
dev = qdev_new("sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
pl011_create(0xfff36000, pic[20], serial_hd(0));
dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
@ -363,18 +363,18 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "xgmac");
dev = qdev_create(NULL, "xgmac");
dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
qemu_check_nic_model(&nd_table[1], "xgmac");
dev = qdev_create(NULL, "xgmac");
dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);

10
hw/arm/imx25_pdk.c
View File

@ -73,10 +73,9 @@ static void imx25_pdk_init(MachineState *machine)
unsigned int alias_offset;
int i;
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_FSL_IMX25, &error_abort, NULL);
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX25);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* We need to initialize our memory */
if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
@ -130,10 +129,9 @@ static void imx25_pdk_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
/*

6
hw/arm/integratorcp.c
View File

@ -607,7 +607,7 @@ static void integratorcp_init(MachineState *machine)
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu = ARM_CPU(cpuobj);
@ -620,9 +620,9 @@ static void integratorcp_init(MachineState *machine)
0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
dev = qdev_new(TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,

5
hw/arm/kzm.c
View File

@ -71,10 +71,9 @@ static void kzm_init(MachineState *machine)
unsigned int alias_offset;
unsigned int i;
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_FSL_IMX31, &error_abort, NULL);
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX31);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Check the amount of memory is compatible with the SOC */
if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {

7
hw/arm/mcimx6ul-evk.c
View File

@ -40,7 +40,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
machine->ram);
@ -54,10 +54,9 @@ static void mcimx6ul_evk_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {

7
hw/arm/mcimx7d-sabre.c
View File

@ -42,7 +42,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
machine->ram);
@ -56,10 +56,9 @@ static void mcimx7d_sabre_init(MachineState *machine)
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {

22
hw/arm/microbit.c
View File

@ -36,30 +36,28 @@ static void microbit_init(MachineState *machine)
MicrobitMachineState *s = MICROBIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mr;
Object *soc = OBJECT(&s->nrf51);
Object *i2c = OBJECT(&s->i2c);
sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
TYPE_NRF51_SOC);
object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51,
TYPE_NRF51_SOC);
qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
object_property_set_link(soc, OBJECT(system_memory), "memory",
&error_fatal);
object_property_set_bool(soc, true, "realized", &error_fatal);
object_property_set_link(OBJECT(&s->nrf51), OBJECT(system_memory),
"memory", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal);
/*
* Overlap the TWI stub device into the SoC. This is a microbit-specific
* hack until we implement the nRF51 TWI controller properly and the
* magnetometer/accelerometer devices.
*/
sysbus_init_child_obj(OBJECT(machine), "microbit.twi", i2c,
sizeof(s->i2c), TYPE_MICROBIT_I2C);
object_property_set_bool(i2c, true, "realized", &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(i2c), 0);
object_initialize_child(OBJECT(machine), "microbit.twi", &s->i2c,
TYPE_MICROBIT_I2C);
sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0);
memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
mr, -1);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
NRF51_SOC(soc)->flash_size);
s->nrf51.flash_size);
}
static void microbit_machine_class_init(ObjectClass *oc, void *data)

79
hw/arm/mps2-tz.c
View File

@ -174,12 +174,10 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
*/
UnimplementedDeviceState *uds = opaque;
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
}
@ -194,11 +192,10 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
SysBusDevice *s;
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
TYPE_CMSDK_APB_UART);
object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
@ -215,13 +212,12 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
DeviceState *sccdev;
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
sysbus_init_child_obj(OBJECT(mms), "scc", scc,
sizeof(mms->scc), TYPE_MPS2_SCC);
object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
sccdev = DEVICE(scc);
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
}
@ -230,9 +226,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
{
MPS2FPGAIO *fpgaio = opaque;
sysbus_init_child_obj(OBJECT(mms), "fpgaio", fpgaio,
sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
}
@ -246,11 +241,11 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
mms->lan9118 = qdev_create(NULL, TYPE_LAN9118);
mms->lan9118 = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(mms->lan9118, nd);
qdev_init_nofail(mms->lan9118);
s = SYS_BUS_DEVICE(mms->lan9118);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
return sysbus_mmio_get_region(s, 0);
}
@ -268,11 +263,10 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
TYPE_TZ_MPC);
object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
@ -311,13 +305,13 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
* the MSC connects to the IoTKit AHB Slave Expansion port, so the
* DMA devices can see all devices and memory that the CPU does.
*/
sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC);
object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
object_property_set_link(OBJECT(msc), OBJECT(msc_downstream),
"downstream", &error_fatal);
object_property_set_link(OBJECT(msc), OBJECT(mms),
"idau", &error_fatal);
object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
qdev_get_gpio_in_named(iotkitdev,
@ -334,10 +328,10 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
"cfg_sec_resp", 0));
msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081);
object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
object_property_set_link(OBJECT(dma), OBJECT(msc_upstream),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
s = SYS_BUS_DEVICE(dma);
/* Wire up DMACINTR, DMACINTERR, DMACINTTC */
@ -364,9 +358,8 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
int i = spi - &mms->spi[0];
SysBusDevice *s;
sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]),
TYPE_PL022);
object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal);
object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
s = SYS_BUS_DEVICE(spi);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
return sysbus_mmio_get_region(s, 0);
@ -395,15 +388,14 @@ static void mps2tz_common_init(MachineState *machine)
exit(EXIT_FAILURE);
}
sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
sizeof(mms->iotkit), mmc->armsse_type);
object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
mmc->armsse_type);
iotkitdev = DEVICE(&mms->iotkit);
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
"memory", &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
/*
* The AN521 needs us to create splitters to feed the IRQ inputs
@ -414,15 +406,15 @@ static void mps2tz_common_init(MachineState *machine)
char *name = g_strdup_printf("mps2-irq-splitter%d", i);
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
object_initialize_child(OBJECT(machine), name,
splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_fatal, NULL);
object_initialize_child_with_props(OBJECT(machine), name,
splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_fatal,
NULL);
g_free(name);
object_property_set_int(OBJECT(splitter), 2, "num-lines",
&error_fatal);
object_property_set_bool(OBJECT(splitter), true, "realized",
&error_fatal);
qdev_realize(DEVICE(splitter), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(splitter), 0,
qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
"EXP_IRQ", i));
@ -436,14 +428,11 @@ static void mps2tz_common_init(MachineState *machine)
* lines, one for each of the PPCs we create here, plus one per MSC.
*/
object_initialize_child(OBJECT(machine), "sec-resp-splitter",
&mms->sec_resp_splitter,
sizeof(mms->sec_resp_splitter),
TYPE_SPLIT_IRQ, &error_abort, NULL);
&mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
"num-lines", &error_fatal);
object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
"realized", &error_fatal);
qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
dev_splitter = DEVICE(&mms->sec_resp_splitter);
qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
@ -472,12 +461,10 @@ static void mps2tz_common_init(MachineState *machine)
* Create the OR gate for this.
*/
object_initialize_child(OBJECT(mms), "uart-irq-orgate",
&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
TYPE_OR_IRQ, &error_abort, NULL);
&mms->uart_irq_orgate, TYPE_OR_IRQ);
object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
&error_fatal);
object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
"realized", &error_fatal);
qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
get_sse_irq_in(mms, 15));
@ -553,8 +540,8 @@ static void mps2tz_common_init(MachineState *machine)
int port;
char *gpioname;
sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
sizeof(TZPPC), TYPE_TZ_PPC);
object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
@ -573,7 +560,7 @@ static void mps2tz_common_init(MachineState *machine)
g_free(portname);
}
object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];

26
hw/arm/mps2.c
View File

@ -180,8 +180,7 @@ static void mps2_common_init(MachineState *machine)
g_assert_not_reached();
}
sysbus_init_child_obj(OBJECT(mms), "armv7m", &mms->armv7m,
sizeof(mms->armv7m), TYPE_ARMV7M);
object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
armv7m = DEVICE(&mms->armv7m);
switch (mmc->fpga_type) {
case FPGA_AN385:
@ -197,8 +196,7 @@ static void mps2_common_init(MachineState *machine)
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
"memory", &error_abort);
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
@ -231,7 +229,7 @@ static void mps2_common_init(MachineState *machine)
orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(orgate, 6, "num-lines", &error_fatal);
object_property_set_bool(orgate, true, "realized", &error_fatal);
qdev_realize(DEVICE(orgate), NULL, &error_fatal);
orgate_dev = DEVICE(orgate);
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
@ -268,7 +266,7 @@ static void mps2_common_init(MachineState *machine)
orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(orgate, 10, "num-lines", &error_fatal);
object_property_set_bool(orgate, true, "realized", &error_fatal);
qdev_realize(DEVICE(orgate), NULL, &error_fatal);
orgate_dev = DEVICE(orgate);
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
@ -283,8 +281,7 @@ static void mps2_common_init(MachineState *machine)
txrx_orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
object_property_set_bool(txrx_orgate, true, "realized",
&error_fatal);
qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
txrx_orgate_dev = DEVICE(txrx_orgate);
qdev_connect_gpio_out(txrx_orgate_dev, 0,
qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
@ -305,23 +302,20 @@ static void mps2_common_init(MachineState *machine)
cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
sysbus_init_child_obj(OBJECT(mms), "dualtimer", &mms->dualtimer,
sizeof(mms->dualtimer), TYPE_CMSDK_APB_DUALTIMER);
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
object_property_set_bool(OBJECT(&mms->dualtimer), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
qdev_get_gpio_in(armv7m, 10));
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
sysbus_init_child_obj(OBJECT(mms), "scc", &mms->scc,
sizeof(mms->scc), TYPE_MPS2_SCC);
object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
sccdev = DEVICE(&mms->scc);
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
object_property_set_bool(OBJECT(&mms->scc), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
/* In hardware this is a LAN9220; the LAN9118 is software compatible

25
hw/arm/msf2-soc.c
View File

@ -71,22 +71,17 @@ static void m2sxxx_soc_initfn(Object *obj)
MSF2State *s = MSF2_SOC(obj);
int i;
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
TYPE_ARMV7M);
object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
TYPE_MSF2_SYSREG);
object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
TYPE_MSS_TIMER);
object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
for (i = 0; i < MSF2_NUM_SPIS; i++) {
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
TYPE_MSS_SPI);
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
}
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
TYPE_MSS_EMAC);
object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
@ -130,7 +125,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -158,7 +153,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
dev = DEVICE(&s->timer);
/* APB0 clock is the timer input clock */
qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -173,7 +168,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
dev = DEVICE(&s->sysreg);
qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -184,7 +179,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < MSF2_NUM_SPIS; i++) {
gchar *bus_name;
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -204,7 +199,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
dev = DEVICE(&s->emac);
object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
"ahb-bus", &error_abort);
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

12
hw/arm/msf2-som.c
View File

@ -47,7 +47,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
SSIBus *spi_bus;
BusState *spi_bus;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ddr = g_new(MemoryRegion, 1);
@ -61,7 +61,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
&error_fatal);
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
dev = qdev_create(NULL, TYPE_MSF2_SOC);
dev = qdev_new(TYPE_MSF2_SOC);
qdev_prop_set_string(dev, "part-name", "M2S010");
qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
@ -77,19 +77,19 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
soc = MSF2_SOC(dev);
/* Attach SPI flash to SPI0 controller */
spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
spi_bus = qdev_get_child_bus(dev, "spi0");
spi_flash = qdev_new("s25sl12801");
qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
if (dinfo) {
qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(spi_flash);
qdev_realize_and_unref(spi_flash, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);

60
hw/arm/musca.c
View File

@ -142,12 +142,10 @@ static MemoryRegion *make_unimp_dev(MuscaMachineState *mms,
*/
UnimplementedDeviceState *uds = opaque;
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
}
@ -246,23 +244,21 @@ static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque,
case MPC_CRYPTOISLAND:
/* We don't implement the CryptoIsland yet */
uds = &mms->cryptoisland;
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(OBJECT(mms), name, uds,
TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name);
qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
break;
default:
g_assert_not_reached();
}
sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->mpc[0]),
TYPE_TZ_MPC);
object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(downstream),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream);
@ -281,8 +277,8 @@ static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque,
{
PL031State *rtc = opaque;
sysbus_init_child_obj(OBJECT(mms), name, rtc, sizeof(mms->rtc), TYPE_PL031);
object_property_set_bool(OBJECT(rtc), true, "realized", &error_fatal);
object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031);
sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39));
return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0);
}
@ -295,10 +291,9 @@ static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque,
int irqbase = 7 + i * 6;
SysBusDevice *s;
sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
TYPE_PL011);
object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */
@ -376,8 +371,8 @@ static void musca_init(MachineState *machine)
exit(1);
}
sysbus_init_child_obj(OBJECT(machine), "sse-200", &mms->sse,
sizeof(mms->sse), TYPE_SSE200);
object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
TYPE_SSE200);
ssedev = DEVICE(&mms->sse);
object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory),
"memory", &error_fatal);
@ -393,8 +388,7 @@ static void musca_init(MachineState *machine)
qdev_prop_set_bit(ssedev, "CPU0_FPU", true);
qdev_prop_set_bit(ssedev, "CPU0_DSP", true);
}
object_property_set_bool(OBJECT(&mms->sse), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal);
/*
* We need to create splitters to feed the IRQ inputs
@ -404,15 +398,14 @@ static void musca_init(MachineState *machine)
char *name = g_strdup_printf("musca-irq-splitter%d", i);
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
object_initialize_child(OBJECT(machine), name,
splitter, sizeof(*splitter),
TYPE_SPLIT_IRQ, &error_fatal, NULL);
object_initialize_child_with_props(OBJECT(machine), name, splitter,
sizeof(*splitter), TYPE_SPLIT_IRQ,
&error_fatal, NULL);
g_free(name);
object_property_set_int(OBJECT(splitter), 2, "num-lines",
&error_fatal);
object_property_set_bool(OBJECT(splitter), true, "realized",
&error_fatal);
qdev_realize(DEVICE(splitter), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(splitter), 0,
qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i));
qdev_connect_gpio_out(DEVICE(splitter), 1,
@ -424,15 +417,14 @@ static void musca_init(MachineState *machine)
* The sec_resp_cfg output from the SSE-200 must be split into multiple
* lines, one for each of the PPCs we create here.
*/
object_initialize_child(OBJECT(machine), "sec-resp-splitter",
&mms->sec_resp_splitter,
sizeof(mms->sec_resp_splitter),
TYPE_SPLIT_IRQ, &error_fatal, NULL);
object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter",
&mms->sec_resp_splitter,
sizeof(mms->sec_resp_splitter),
TYPE_SPLIT_IRQ, &error_fatal, NULL);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
"realized", &error_fatal);
qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
dev_splitter = DEVICE(&mms->sec_resp_splitter);
qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
@ -534,8 +526,8 @@ static void musca_init(MachineState *machine)
int port;
char *gpioname;
sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
sizeof(TZPPC), TYPE_TZ_PPC);
object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
@ -554,7 +546,7 @@ static void musca_init(MachineState *machine)
g_free(portname);
}
object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];

8
hw/arm/musicpal.c
View File

@ -1651,9 +1651,9 @@ static void musicpal_init(MachineState *machine)
sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_create(NULL, TYPE_MV88W8618_ETH);
dev = qdev_new(TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
@ -1688,11 +1688,11 @@ static void musicpal_init(MachineState *machine)
}
wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR);
dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO);
dev = qdev_new(TYPE_MV88W8618_AUDIO);
s = SYS_BUS_DEVICE(dev);
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
"wm8750", NULL);
qdev_init_nofail(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);

4
hw/arm/netduino2.c
View File

@ -34,9 +34,9 @@ static void netduino2_init(MachineState *machine)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
FLASH_SIZE);

4
hw/arm/netduinoplus2.c
View File

@ -34,9 +34,9 @@ static void netduinoplus2_init(MachineState *machine)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_STM32F405_SOC);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,

30
hw/arm/nrf51_soc.c
View File

@ -71,7 +71,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err);
if (err) {
error_propagate(errp, err);
return;
@ -88,7 +88,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
/* UART */
object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
if (err) {
error_propagate(errp, err);
return;
@ -100,7 +100,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
BASE_TO_IRQ(NRF51_UART_BASE)));
/* RNG */
object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err);
if (err) {
error_propagate(errp, err);
return;
@ -120,7 +120,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err);
if (err) {
error_propagate(errp, err);
return;
@ -136,7 +136,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
@ -155,7 +155,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -189,27 +189,23 @@ static void nrf51_soc_init(Object *obj)
memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
TYPE_ARMV7M);
object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
TYPE_NRF51_UART);
object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
TYPE_NRF51_RNG);
object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
TYPE_NRF51_GPIO);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
sizeof(s->timer[i]), TYPE_NRF51_TIMER);
object_initialize_child(obj, "timer[*]", &s->timer[i],
TYPE_NRF51_TIMER);
}
}

8
hw/arm/nseries.c
View File

@ -174,7 +174,7 @@ static void n8x0_nand_setup(struct n800_s *s)
char *otp_region;
DriveInfo *dinfo;
s->nand = qdev_create(NULL, "onenand");
s->nand = qdev_new("onenand");
qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
/* Either 0x40 or 0x48 are OK for the device ID */
qdev_prop_set_uint16(s->nand, "device_id", 0x48);
@ -185,7 +185,7 @@ static void n8x0_nand_setup(struct n800_s *s)
qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(s->nand);
sysbus_realize_and_unref(SYS_BUS_DEVICE(s->nand), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
@ -802,9 +802,9 @@ static void n8x0_uart_setup(struct n800_s *s)
static void n8x0_usb_setup(struct n800_s *s)
{
SysBusDevice *dev;
s->usb = qdev_create(NULL, "tusb6010");
s->usb = qdev_new("tusb6010");
dev = SYS_BUS_DEVICE(s->usb);
qdev_init_nofail(s->usb);
sysbus_realize_and_unref(dev, &error_fatal);
sysbus_connect_irq(dev, 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
/* Using the NOR interface */

16
hw/arm/omap1.c
View File

@ -3887,21 +3887,21 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
s->ih[0] = qdev_create(NULL, "omap-intc");
s->ih[0] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
sysbus_mmio_map(busdev, 0, 0xfffecb00);
s->ih[1] = qdev_create(NULL, "omap-intc");
s->ih[1] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[1]);
busdev = SYS_BUS_DEVICE(s->ih[1]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
/* The second interrupt controller's FIQ output is not wired up */
@ -4010,10 +4010,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
s->wakeup, omap_findclk(s, "clk32-kHz"));
s->gpio = qdev_create(NULL, "omap-gpio");
s->gpio = qdev_new("omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
@ -4028,11 +4028,11 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
omap_findclk(s, "armxor_ck"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);

16
hw/arm/omap2.c
View File

@ -2306,12 +2306,12 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
s->ih[0] = qdev_create(NULL, "omap2-intc");
s->ih[0] = qdev_new("omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
@ -2423,31 +2423,31 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
omap_findclk(s, "clk32-kHz"),
omap_findclk(s, "core_l4_iclk"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
s->i2c[1] = qdev_create(NULL, "omap_i2c");
s->i2c[1] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
qdev_init_nofail(s->i2c[1]);
busdev = SYS_BUS_DEVICE(s->i2c[1]);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
s->gpio = qdev_create(NULL, "omap2-gpio");
s->gpio = qdev_new("omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
@ -2458,8 +2458,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
omap_findclk(s, "gpio5_dbclk"));
}
qdev_init_nofail(s->gpio);
busdev = SYS_BUS_DEVICE(s->gpio);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
sysbus_connect_irq(busdev, 3,

6
hw/arm/orangepi.c
View File

@ -86,7 +86,7 @@ static void orangepi_init(MachineState *machine)
&error_abort);
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
qdev_realize(DEVICE(h3), NULL, &error_abort);
/* Retrieve SD bus */
di = drive_get_next(IF_SD);
@ -94,9 +94,9 @@ static void orangepi_init(MachineState *machine)
bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
/* Plug in SD card */
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],

8
hw/arm/pxa2xx.c
View File

@ -1510,12 +1510,12 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
PXA2xxI2CState *s;
I2CBus *i2cbus;
dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
dev = qdev_new(TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
qdev_prop_set_uint32(dev, "offset", base & region_size);
qdev_init_nofail(dev);
i2c_dev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(i2c_dev, &error_fatal);
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
sysbus_connect_irq(i2c_dev, 0, irq);
@ -2073,10 +2073,10 @@ static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
DeviceState *dev;
SysBusDevice *sbd;
dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
dev = qdev_new(TYPE_PXA2XX_FIR);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);
sysbus_connect_irq(sbd, 1, rx_dma);

5
hw/arm/pxa2xx_gpio.c
View File

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
@ -269,10 +270,10 @@ DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUState *cs = CPU(cpu);
DeviceState *dev;
dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
dev = qdev_new(TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

5
hw/arm/pxa2xx_pic.c
View File

@ -9,6 +9,7 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "cpu.h"
#include "hw/arm/pxa.h"
@ -267,7 +268,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
PXA2xxPICState *s = PXA2XX_PIC(dev);
s->cpu = cpu;
@ -279,7 +280,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);

10
hw/arm/raspi.c
View File

@ -282,12 +282,12 @@ static void raspi_machine_init(MachineState *machine)
machine->ram, 0);
/* Setup the SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
board_soc_type(board_rev), &error_abort, NULL);
object_initialize_child(OBJECT(machine), "soc", &s->soc,
board_soc_type(board_rev));
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram));
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
&error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Create and plug in the SD cards */
di = drive_get_next(IF_SD);
@ -297,9 +297,9 @@ static void raspi_machine_init(MachineState *machine)
error_report("No SD bus found in SOC object");
exit(1);
}
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
&error_abort);

22
hw/arm/realview.c
View File

@ -114,7 +114,7 @@ static void realview_init(MachineState *machine,
&error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
}
@ -161,17 +161,17 @@ static void realview_init(MachineState *machine,
}
sys_id = is_pb ? 0x01780500 : 0xc1400400;
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
qdev_init_nofail(sysctl);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
if (is_mpcore) {
dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
@ -188,9 +188,9 @@ static void realview_init(MachineState *machine,
pic[n] = qdev_get_gpio_in(dev, n);
}
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
@ -203,11 +203,11 @@ static void realview_init(MachineState *machine,
pl011_create(0x1000c000, pic[15], serial_hd(3));
/* DMA controller is optional, apparently. */
dev = qdev_create(NULL, "pl081");
dev = qdev_new("pl081");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10030000);
sysbus_connect_irq(busdev, 0, pic[24]);
@ -239,9 +239,9 @@ static void realview_init(MachineState *machine,
sysbus_create_simple("pl031", 0x10017000, pic[10]);
if (!is_pb) {
dev = qdev_create(NULL, "realview_pci");
dev = qdev_new("realview_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */

6
hw/arm/sabrelite.c
View File

@ -51,7 +51,7 @@ static void sabrelite_init(MachineState *machine)
s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
machine->ram);
@ -75,13 +75,13 @@ static void sabrelite_init(MachineState *machine)
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
flash_dev = ssi_create_slave_no_init(spi_bus, "sst25vf016b");
flash_dev = qdev_new("sst25vf016b");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive",
blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(flash_dev);
qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);

26
hw/arm/sbsa-ref.c
View File

@ -211,7 +211,7 @@ static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
* Create a single flash device. We use the same parameters as
* the flash devices on the Versatile Express board.
*/
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
@ -243,7 +243,7 @@ static void sbsa_flash_map1(PFlashCFI01 *flash,
assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
@ -339,7 +339,7 @@ static void create_gic(SBSAMachineState *sms)
gictype = gicv3_class_name();
sms->gic = qdev_create(NULL, gictype);
sms->gic = qdev_new(gictype);
qdev_prop_set_uint32(sms->gic, "revision", 3);
qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
/*
@ -356,8 +356,8 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
qdev_init_nofail(sms->gic);
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
@ -409,11 +409,11 @@ static void create_uart(const SBSAMachineState *sms, int uart,
{
hwaddr base = sbsa_ref_memmap[uart].base;
int irq = sbsa_ref_irqmap[uart];
DeviceState *dev = qdev_create(NULL, TYPE_PL011);
DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
@ -464,9 +464,9 @@ static void create_ahci(const SBSAMachineState *sms)
AHCIState *ahci;
int i;
dev = qdev_create(NULL, "sysbus-ahci");
dev = qdev_new("sysbus-ahci");
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
@ -497,11 +497,11 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
DeviceState *dev;
int i;
dev = qdev_create(NULL, "arm-smmuv3");
dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -525,8 +525,8 @@ static void create_pcie(SBSAMachineState *sms)
PCIHostState *pci;
int i;
dev = qdev_create(NULL, TYPE_GPEX_HOST);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_GPEX_HOST);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Map ECAM space */
ecam_alias = g_new0(MemoryRegion, 1);
@ -680,7 +680,7 @@ static void sbsa_ref_init(MachineState *machine)
object_property_set_link(cpuobj, OBJECT(secure_sysmem),
"secure-memory", &error_abort);
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
object_unref(cpuobj);
}

4
hw/arm/spitz.c
View File

@ -155,7 +155,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_SL_NAND);
dev = qdev_new(TYPE_SL_NAND);
qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
if (size == FLASH_128M)
@ -163,7 +163,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
else if (size == FLASH_1024M)
qdev_prop_set_uint8(dev, "chip_id", 0xf1);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}

12
hw/arm/stellaris.c
View File

@ -1308,14 +1308,14 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
&error_fatal);
memory_region_add_subregion(system_memory, 0x20000000, sram);
nvic = qdev_create(NULL, TYPE_ARMV7M);
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
qdev_init_nofail(nvic);
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
qemu_allocate_irq(&do_sys_reset, NULL, 0));
@ -1347,13 +1347,13 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
if (board->dc1 & (1 << 3)) { /* watchdog present */
dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
/* system_clock_scale is valid now */
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
0,
0x40000000u);
@ -1425,9 +1425,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qemu_check_nic_model(&nd_table[0], "stellaris");
enet = qdev_create(NULL, "stellaris_enet");
enet = qdev_new("stellaris_enet");
qdev_set_nic_properties(enet, &nd_table[0]);
qdev_init_nofail(enet);
sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
}

34
hw/arm/stm32f205_soc.c
View File

@ -51,32 +51,28 @@ static void stm32f205_soc_initfn(Object *obj)
STM32F205State *s = STM32F205_SOC(obj);
int i;
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
TYPE_ARMV7M);
object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
TYPE_STM32F2XX_SYSCFG);
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
for (i = 0; i < STM_NUM_USARTS; i++) {
sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
object_initialize_child(obj, "usart[*]", &s->usart[i],
TYPE_STM32F2XX_USART);
}
for (i = 0; i < STM_NUM_TIMERS; i++) {
sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
object_initialize_child(obj, "timer[*]", &s->timer[i],
TYPE_STM32F2XX_TIMER);
}
s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
for (i = 0; i < STM_NUM_ADCS; i++) {
sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
TYPE_STM32F2XX_ADC);
object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
}
for (i = 0; i < STM_NUM_SPIS; i++) {
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
TYPE_STM32F2XX_SPI);
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
}
@ -111,7 +107,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -119,7 +115,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
/* System configuration controller */
dev = DEVICE(&s->syscfg);
object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -132,7 +128,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < STM_NUM_USARTS; i++) {
dev = DEVICE(&(s->usart[i]));
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -146,7 +142,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < STM_NUM_TIMERS; i++) {
dev = DEVICE(&(s->timer[i]));
qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -159,7 +155,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
/* ADC 1 to 3 */
object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
"num-lines", &err);
object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
qdev_realize(DEVICE(s->adc_irqs), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -169,7 +165,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < STM_NUM_ADCS; i++) {
dev = DEVICE(&(s->adc[i]));
object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -183,7 +179,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
/* SPI 1 and 2 */
for (i = 0; i < STM_NUM_SPIS; i++) {
dev = DEVICE(&(s->spi[i]));
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

66
hw/arm/stm32f405_soc.c
View File

@ -37,7 +37,8 @@ static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
/* At the moment only Timer 2 to 5 are modelled */
static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
0x40000800, 0x40000C00 };
#define ADC_ADDR 0x40012000
static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
0x40012300, 0x40012400, 0x40012500 };
static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
0x40013400, 0x40015000, 0x40015400 };
#define EXTI_ADDR 0x40013C00
@ -56,34 +57,29 @@ static void stm32f405_soc_initfn(Object *obj)
STM32F405State *s = STM32F405_SOC(obj);
int i;
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
TYPE_ARMV7M);
object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
TYPE_STM32F4XX_SYSCFG);
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
for (i = 0; i < STM_NUM_USARTS; i++) {
sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
object_initialize_child(obj, "usart[*]", &s->usart[i],
TYPE_STM32F2XX_USART);
}
for (i = 0; i < STM_NUM_TIMERS; i++) {
sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
object_initialize_child(obj, "timer[*]", &s->timer[i],
TYPE_STM32F2XX_TIMER);
}
for (i = 0; i < STM_NUM_ADCS; i++) {
sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
TYPE_STM32F2XX_ADC);
object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
}
for (i = 0; i < STM_NUM_SPIS; i++) {
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
TYPE_STM32F2XX_SPI);
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
TYPE_STM32F4XX_EXTI);
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
}
static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
@ -122,7 +118,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -130,7 +126,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
/* System configuration controller */
dev = DEVICE(&s->syscfg);
object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -143,7 +139,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < STM_NUM_USARTS; i++) {
dev = DEVICE(&(s->usart[i]));
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -157,7 +153,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
for (i = 0; i < STM_NUM_TIMERS; i++) {
dev = DEVICE(&(s->timer[i]));
qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -168,16 +164,16 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
}
/* ADC device, the IRQs are ORed together */
object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
sizeof(s->adc_irqs), TYPE_OR_IRQ,
&err, NULL);
object_initialize_child_with_props(OBJECT(s), "adc-orirq", &s->adc_irqs,
sizeof(s->adc_irqs), TYPE_OR_IRQ, &err,
NULL);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
"num-lines", &err);
object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
qdev_realize(DEVICE(&s->adc_irqs), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -185,21 +181,23 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
qdev_get_gpio_in(armv7m, ADC_IRQ));
dev = DEVICE(&(s->adc[i]));
object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_ADCS; i++) {
dev = DEVICE(&(s->adc[i]));
sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, adc_addr[i]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
}
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, ADC_ADDR);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
/* SPI devices */
for (i = 0; i < STM_NUM_SPIS; i++) {
dev = DEVICE(&(s->spi[i]));
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -211,7 +209,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
/* EXTI device */
dev = DEVICE(&s->exti);
object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->exti), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

9
hw/arm/strongarm.c
View File

@ -42,6 +42,7 @@
#include "chardev/char-serial.h"
#include "sysemu/sysemu.h"
#include "hw/ssi/ssi.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
@ -644,8 +645,8 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
DeviceState *dev;
int i;
dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_STRONGARM_GPIO);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < 12; i++)
@ -1626,9 +1627,9 @@ StrongARMState *sa1110_init(const char *cpu_type)
s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
for (i = 0; sa_serial[i].io_base; i++) {
DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
DeviceState *dev = qdev_new(TYPE_STRONGARM_UART);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
sa_serial[i].io_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

18
hw/arm/versatilepb.c
View File

@ -215,7 +215,7 @@ static void versatile_init(MachineState *machine, int board_id)
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu = ARM_CPU(cpuobj);
@ -223,10 +223,10 @@ static void versatile_init(MachineState *machine, int board_id)
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, machine->ram);
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
qdev_init_nofail(sysctl);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
dev = sysbus_create_varargs("pl190", 0x10140000,
@ -245,9 +245,9 @@ static void versatile_init(MachineState *machine, int board_id)
sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
dev = qdev_create(NULL, "versatile_pci");
dev = qdev_new("versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
@ -286,11 +286,11 @@ static void versatile_init(MachineState *machine, int board_id)
pl011_create(0x101f3000, pic[14], serial_hd(2));
pl011_create(0x10009000, sic[6], serial_hd(3));
dev = qdev_create(NULL, "pl080");
dev = qdev_new("pl080");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10130000);
sysbus_connect_irq(busdev, 0, pic[17]);
@ -319,9 +319,9 @@ static void versatile_init(MachineState *machine, int board_id)
i2c_create_slave(i2c, "ds1338", 0x68);
/* Add PL041 AACI Interface to the LM4549 codec */
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);

18
hw/arm/vexpress.c
View File

@ -229,17 +229,17 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
object_property_set_int(cpuobj, periphbase,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
}
/* Create the private peripheral devices (including the GIC);
* this must happen after the CPUs are created because a15mpcore_priv
* wires itself up to the CPU's generic_timer gpio out lines.
*/
dev = qdev_create(NULL, privdev);
dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
/* Interrupts [42:0] are from the motherboard;
@ -514,7 +514,7 @@ static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
DriveInfo *di)
{
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
if (di) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
@ -532,7 +532,7 @@ static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
@ -593,7 +593,7 @@ static void vexpress_common_init(MachineState *machine)
sys_id = 0x1190f500;
sysctl = qdev_create(NULL, "realview_sysctl");
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
@ -610,15 +610,15 @@ static void vexpress_common_init(MachineState *machine)
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
qdev_init_nofail(sysctl);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
/* VE_SERIALPCI: not modelled */
pl041 = qdev_create(NULL, "pl041");
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);

38
hw/arm/virt.c
View File

@ -572,14 +572,14 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
}
dev = qdev_create(NULL, TYPE_ACPI_GED);
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
@ -594,11 +594,11 @@ static void create_its(VirtMachineState *vms)
return;
}
dev = qdev_create(NULL, itsclass);
dev = qdev_new(itsclass);
object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3",
&error_abort);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
fdt_add_its_gic_node(vms);
@ -610,11 +610,11 @@ static void create_v2m(VirtMachineState *vms)
int irq = vms->irqmap[VIRT_GIC_V2M];
DeviceState *dev;
dev = qdev_create(NULL, "arm-gicv2m");
dev = qdev_new("arm-gicv2m");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -636,7 +636,7 @@ static void create_gic(VirtMachineState *vms)
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
vms->gic = qdev_create(NULL, gictype);
vms->gic = qdev_new(gictype);
qdev_prop_set_uint32(vms->gic, "revision", type);
qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
/* Note that the num-irq property counts both internal and external
@ -671,8 +671,8 @@ static void create_gic(VirtMachineState *vms)
vms->virt);
}
}
qdev_init_nofail(vms->gic);
gicbusdev = SYS_BUS_DEVICE(vms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
if (type == 3) {
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
@ -754,11 +754,11 @@ static void create_uart(const VirtMachineState *vms, int uart,
int irq = vms->irqmap[uart];
const char compat[] = "arm,pl011\0arm,primecell";
const char clocknames[] = "uartclk\0apb_pclk";
DeviceState *dev = qdev_create(NULL, TYPE_PL011);
DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
@ -948,7 +948,7 @@ static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
* Create a single flash device. We use the same parameters as
* the flash devices on the Versatile Express board.
*/
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
@ -980,7 +980,7 @@ static void virt_flash_map1(PFlashCFI01 *flash,
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
@ -1173,11 +1173,11 @@ static void create_smmu(const VirtMachineState *vms,
return;
}
dev = qdev_create(NULL, "arm-smmuv3");
dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
@ -1253,8 +1253,8 @@ static void create_pcie(VirtMachineState *vms)
int i, ecam_id;
PCIHostState *pci;
dev = qdev_create(NULL, TYPE_GPEX_HOST);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_GPEX_HOST);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
base_ecam = vms->memmap[ecam_id].base;
@ -1372,11 +1372,11 @@ static void create_platform_bus(VirtMachineState *vms)
int i;
MemoryRegion *sysmem = get_system_memory();
dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
vms->platform_bus_dev = dev;
s = SYS_BUS_DEVICE(dev);
@ -1819,7 +1819,7 @@ static void machvirt_init(MachineState *machine)
"secure-memory", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
object_unref(cpuobj);
}
fdt_add_timer_nodes(vms);

44
hw/arm/xilinx_zynq.c
View File

@ -114,13 +114,13 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, TYPE_CADENCE_GEM);
dev = qdev_new(TYPE_CADENCE_GEM);
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
@ -136,12 +136,12 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base_addr);
if (is_qspi) {
sysbus_mmio_map(busdev, 1, 0xFC000000);
@ -157,12 +157,12 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
for (j = 0; j < num_ss; ++j) {
DriveInfo *dinfo = drive_get_next(IF_MTD);
flash_dev = ssi_create_slave_no_init(spi, "n25q128");
flash_dev = qdev_new("n25q128");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive",
blk_by_legacy_dinfo(dinfo), &error_fatal);
}
qdev_init_nofail(flash_dev);
qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
@ -202,7 +202,7 @@ static void zynq_init(MachineState *machine)
&error_fatal);
object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
&error_fatal);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
qdev_realize(DEVICE(cpu), NULL, &error_fatal);
/* DDR remapped to address zero. */
memory_region_add_subregion(address_space_mem, 0, machine->ram);
@ -222,8 +222,8 @@ static void zynq_init(MachineState *machine)
0);
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_create(NULL, "xilinx,zynq_slcr");
qdev_init_nofail(slcr);
slcr = qdev_new("xilinx,zynq_slcr");
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
/* Create the main clock source, and feed slcr with it */
@ -234,10 +234,10 @@ static void zynq_init(MachineState *machine)
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
@ -280,27 +280,27 @@ static void zynq_init(MachineState *machine)
* - SDIO Specification Version 2.0
* - MMC Specification Version 3.31
*/
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
dev = qdev_new(TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
&error_fatal);
}
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_ZYNQ_XADC);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
dev = qdev_create(NULL, "pl330");
dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", 4);
qdev_prop_set_uint8(dev, "num_events", 16);
@ -312,17 +312,17 @@ static void zynq_init(MachineState *machine)
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xF8003000);
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
}
dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
qdev_init_nofail(dev);
dev = qdev_new("xlnx.ps7-dev-cfg");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);

15
hw/arm/xlnx-versal-virt.c
View File

@ -432,9 +432,9 @@ static void create_virtio_regions(VersalVirt *s)
qemu_irq pic_irq;
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
dev = qdev_create(NULL, "virtio-mmio");
dev = qdev_new("virtio-mmio");
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
@ -463,10 +463,11 @@ static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
DeviceState *card;
card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
card = qdev_new(TYPE_SD_CARD);
object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card));
qdev_prop_set_drive(card, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"),
&error_fatal);
}
static void versal_virt_init(MachineState *machine)
@ -499,13 +500,13 @@ static void versal_virt_init(MachineState *machine)
psci_conduit = QEMU_PSCI_CONDUIT_SMC;
}
sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
sizeof(s->soc), TYPE_XLNX_VERSAL);
object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc,
TYPE_XLNX_VERSAL);
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr", &error_abort);
object_property_set_int(OBJECT(&s->soc), psci_conduit,
"psci-conduit", &error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
fdt_create(s);
create_virtio_regions(s);

53
hw/arm/xlnx-versal.c
View File

@ -32,9 +32,8 @@ static void versal_create_apu_cpus(Versal *s)
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
Object *obj;
object_initialize_child(OBJECT(s), "apu-cpu[*]",
&s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
XLNX_VERSAL_ACPU_TYPE);
obj = OBJECT(&s->fpd.apu.cpu[i]);
object_property_set_int(obj, s->cfg.psci_conduit,
"psci-conduit", &error_abort);
@ -48,7 +47,7 @@ static void versal_create_apu_cpus(Versal *s)
"core-count", &error_abort);
object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
&error_abort);
object_property_set_bool(obj, true, "realized", &error_fatal);
qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
}
@ -63,9 +62,8 @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
int i;
sysbus_init_child_obj(OBJECT(s), "apu-gic",
&s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
gicv3_class_name());
object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
gicv3_class_name());
gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
gicdev = DEVICE(&s->fpd.apu.gic);
qdev_prop_set_uint32(gicdev, "revision", 3);
@ -75,8 +73,7 @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
qdev_prop_set_bit(gicdev, "has-security-extensions", true);
object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
for (i = 0; i < ARRAY_SIZE(addrs); i++) {
MemoryRegion *mr;
@ -134,12 +131,11 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
DeviceState *dev;
MemoryRegion *mr;
sysbus_init_child_obj(OBJECT(s), name,
&s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
TYPE_PL011);
object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
TYPE_PL011);
dev = DEVICE(&s->lpd.iou.uart[i]);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
qdev_init_nofail(dev);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
@ -161,9 +157,8 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
DeviceState *dev;
MemoryRegion *mr;
sysbus_init_child_obj(OBJECT(s), name,
&s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
TYPE_CADENCE_GEM);
object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
TYPE_CADENCE_GEM);
dev = DEVICE(&s->lpd.iou.gem[i]);
if (nd->used) {
qemu_check_nic_model(nd, "cadence_gem");
@ -175,7 +170,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
object_property_set_link(OBJECT(dev),
OBJECT(&s->mr_ps), "dma",
&error_abort);
qdev_init_nofail(dev);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
@ -194,12 +189,11 @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
DeviceState *dev;
MemoryRegion *mr;
sysbus_init_child_obj(OBJECT(s), name,
&s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
TYPE_XLNX_ZDMA);
object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
TYPE_XLNX_ZDMA);
dev = DEVICE(&s->lpd.iou.adma[i]);
object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
qdev_init_nofail(dev);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps,
@ -219,9 +213,8 @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
DeviceState *dev;
MemoryRegion *mr;
sysbus_init_child_obj(OBJECT(s), "sd[*]",
&s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
TYPE_SYSBUS_SDHCI);
object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
TYPE_SYSBUS_SDHCI);
dev = DEVICE(&s->pmc.iou.sd[i]);
object_property_set_uint(OBJECT(dev),
@ -229,7 +222,7 @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
&error_fatal);
object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
qdev_init_nofail(dev);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps,
@ -245,10 +238,10 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
SysBusDevice *sbd;
MemoryRegion *mr;
sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
TYPE_XLNX_ZYNQMP_RTC);
object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
TYPE_XLNX_ZYNQMP_RTC);
sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
qdev_init_nofail(DEVICE(sbd));
sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal);
mr = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
@ -304,13 +297,13 @@ static void versal_unimp_area(Versal *s, const char *name,
MemoryRegion *mr,
hwaddr base, hwaddr size)
{
DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
MemoryRegion *mr_dev;
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
object_property_add_child(OBJECT(s), name, OBJECT(dev));
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(mr, base, mr_dev);

26
hw/arm/xlnx-zcu102.c
View File

@ -116,8 +116,7 @@ static void xlnx_zcu102_init(MachineState *machine)
ram_size);
}
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_XLNX_ZYNQMP, &error_abort, NULL);
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr-ram", &error_abort);
@ -126,7 +125,7 @@ static void xlnx_zcu102_init(MachineState *machine)
object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
&error_fatal);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Create and plug in the SD cards */
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
@ -143,28 +142,27 @@ static void xlnx_zcu102_init(MachineState *machine)
error_report("No SD bus found for SD card %d", i);
exit(1);
}
carddev = qdev_create(bus, TYPE_SD_CARD);
carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
qdev_realize_and_unref(carddev, bus, &error_fatal);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
SSIBus *spi_bus;
BusState *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
gchar *bus_name = g_strdup_printf("spi%d", i);
spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
flash_dev = qdev_new("sst25wf080");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(flash_dev);
qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
@ -172,22 +170,22 @@ static void xlnx_zcu102_init(MachineState *machine)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
SSIBus *spi_bus;
BusState *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
gchar *bus_name = g_strdup_printf("qspi%d", bus);
spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
flash_dev = qdev_new("n25q512a11");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(flash_dev);
qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);

92
hw/arm/xlnx-zynqmp.c
View File

@ -187,17 +187,15 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
}
object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER,
&error_abort, NULL);
TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
for (i = 0; i < num_rpus; i++) {
char *name;
object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
ARM_CPU_TYPE_NAME("cortex-r5f"),
&error_abort, NULL);
&s->rpu_cpu[i],
ARM_CPU_TYPE_NAME("cortex-r5f"));
name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
if (strcmp(name, boot_cpu)) {
@ -211,15 +209,14 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
&error_abort);
object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
&err);
qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
}
qdev_init_nofail(DEVICE(&s->rpu_cluster));
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
}
static void xlnx_zynqmp_init(Object *obj)
@ -230,65 +227,53 @@ static void xlnx_zynqmp_init(Object *obj)
int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
sizeof(s->apu_cluster), TYPE_CPU_CLUSTER,
&error_abort, NULL);
TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
for (i = 0; i < num_apus; i++) {
object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
ARM_CPU_TYPE_NAME("cortex-a53"),
&error_abort, NULL);
&s->apu_cpu[i],
ARM_CPU_TYPE_NAME("cortex-a53"));
}
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
gic_class_name());
object_initialize_child(obj, "gic", &s->gic, gic_class_name());
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
TYPE_CADENCE_UART);
object_initialize_child(obj, "uart[*]", &s->uart[i],
TYPE_CADENCE_UART);
}
sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
TYPE_SYSBUS_AHCI);
object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
TYPE_SYSBUS_SDHCI);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
TYPE_XILINX_SPIPS);
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
}
sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
TYPE_XLNX_ZYNQMP_QSPIPS);
object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
TYPE_XLNX_DPDMA);
object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
TYPE_XLNX_ZYNQMP_IPI);
object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
TYPE_XLNX_ZYNQMP_RTC);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
TYPE_XLNX_ZDMA);
object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
TYPE_XLNX_ZDMA);
object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
}
}
@ -355,7 +340,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(DEVICE(&s->gic),
"has-virtualization-extensions", s->virt);
qdev_init_nofail(DEVICE(&s->apu_cluster));
qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
/* Realize APUs before realizing the GIC. KVM requires this. */
for (i = 0; i < num_apus; i++) {
@ -382,15 +367,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
"reset-cbar", &error_abort);
object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
"core-count", &error_abort);
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
&err);
qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
}
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err) {
error_propagate(errp, err);
return;
@ -486,7 +470,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
&error_abort);
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -498,7 +482,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -510,7 +494,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
&error_abort);
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
if (err) {
error_propagate(errp, err);
return;
@ -544,7 +528,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(sdhci, true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
@ -561,7 +545,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
gchar *bus_name;
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -578,7 +562,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
g_free(bus_name);
}
object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err);
if (err) {
error_propagate(errp, err);
return;
@ -600,7 +584,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
g_free(target_bus);
}
object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err);
if (err) {
error_propagate(errp, err);
return;
@ -608,7 +592,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err);
if (err) {
error_propagate(errp, err);
return;
@ -618,7 +602,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err);
if (err) {
error_propagate(errp, err);
return;
@ -626,7 +610,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
@ -640,7 +624,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err);
if (err) {
error_propagate(errp, err);
return;
@ -652,7 +636,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err);
if (err) {
error_propagate(errp, err);
return;

4
hw/audio/intel-hda.c
View File

@ -1309,8 +1309,8 @@ static int intel_hda_and_codec_init(PCIBus *bus)
controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
hdabus = QLIST_FIRST(&controller->child_bus);
codec = qdev_create(hdabus, "hda-duplex");
qdev_init_nofail(codec);
codec = qdev_new("hda-duplex");
qdev_realize_and_unref(codec, hdabus, &error_fatal);
return 0;
}

16
hw/block/fdc.c
View File

@ -2516,7 +2516,7 @@ static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
continue;
}
dev = qdev_create(&fdctrl->bus.bus, "floppy");
dev = qdev_new("floppy");
qdev_prop_set_uint32(dev, "unit", i);
qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
@ -2531,7 +2531,7 @@ static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
return;
}
object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
qdev_realize_and_unref(dev, &fdctrl->bus.bus, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@ -2544,7 +2544,7 @@ ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
DeviceState *dev;
ISADevice *isadev;
isadev = isa_try_create(bus, TYPE_ISA_FDC);
isadev = isa_try_new(TYPE_ISA_FDC);
if (!isadev) {
return NULL;
}
@ -2558,7 +2558,7 @@ ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
&error_fatal);
}
qdev_init_nofail(dev);
isa_realize_and_unref(isadev, bus, &error_fatal);
return isadev;
}
@ -2571,7 +2571,7 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
SysBusDevice *sbd;
FDCtrlSysBus *sys;
dev = qdev_create(NULL, "sysbus-fdc");
dev = qdev_new("sysbus-fdc");
sys = SYSBUS_FDC(dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
@ -2583,8 +2583,8 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
&error_fatal);
}
qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_connect_irq(sbd, 0, irq);
sysbus_mmio_map(sbd, 0, mmio_base);
}
@ -2595,12 +2595,12 @@ void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DeviceState *dev;
FDCtrlSysBus *sys;
dev = qdev_create(NULL, "SUNW,fdtwo");
dev = qdev_new("SUNW,fdtwo");
if (fds[0]) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
&error_fatal);
}
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sys = SYSBUS_FDC(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);

4
hw/block/nand.c
View File

@ -644,14 +644,14 @@ DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id)
if (nand_flash_ids[chip_id].size == 0) {
hw_error("%s: Unsupported NAND chip ID.\n", __func__);
}
dev = DEVICE(object_new(TYPE_NAND));
dev = qdev_new(TYPE_NAND);
qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
qdev_prop_set_uint8(dev, "chip_id", chip_id);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_fatal);
}
qdev_init_nofail(dev);
qdev_realize(dev, NULL, &error_fatal);
return dev;
}

4
hw/block/pflash_cfi01.c
View File

@ -959,7 +959,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base,
uint16_t id2, uint16_t id3,
int be)
{
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_abort);
@ -974,7 +974,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base,
qdev_prop_set_uint16(dev, "id2", id2);
qdev_prop_set_uint16(dev, "id3", id3);
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);

4
hw/block/pflash_cfi02.c
View File

@ -998,7 +998,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base,
uint16_t unlock_addr1,
int be)
{
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_abort);
@ -1016,7 +1016,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base,
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI02(dev);

4
hw/block/xen-block.c
View File

@ -937,7 +937,7 @@ static void xen_block_device_create(XenBackendInstance *backend,
goto fail;
}
xendev = XEN_DEVICE(qdev_create(BUS(xenbus), type));
xendev = XEN_DEVICE(qdev_new(type));
blockdev = XEN_BLOCK_DEVICE(xendev);
object_property_set_str(OBJECT(xendev), vdev, "vdev", &local_err);
@ -965,7 +965,7 @@ static void xen_block_device_create(XenBackendInstance *backend,
blockdev->iothread = iothread;
blockdev->drive = drive;
object_property_set_bool(OBJECT(xendev), true, "realized", &local_err);
qdev_realize_and_unref(DEVICE(xendev), BUS(xenbus), &local_err);
if (local_err) {
error_propagate_prepend(errp, local_err,
"realization of device %s failed: ",

5
hw/char/exynos4210_uart.c
View File

@ -22,6 +22,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qemu/timer.h"
@ -652,7 +653,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr,
DeviceState *dev;
SysBusDevice *bus;
dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
dev = qdev_new(TYPE_EXYNOS4210_UART);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_prop_set_uint32(dev, "channel", channel);
@ -660,7 +661,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr,
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
bus = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_realize_and_unref(bus, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}

5
hw/char/mcf_uart.c
View File

@ -10,6 +10,7 @@
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "chardev/char-fe.h"
@ -343,11 +344,11 @@ void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_MCF_UART);
dev = qdev_new(TYPE_MCF_UART);
if (chrdrv) {
qdev_prop_set_chr(dev, "chardev", chrdrv);
}
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

5
hw/char/parallel-isa.c
View File

@ -14,17 +14,18 @@
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "hw/char/parallel.h"
#include "qapi/error.h"
static void parallel_init(ISABus *bus, int index, Chardev *chr)
{
DeviceState *dev;
ISADevice *isadev;
isadev = isa_create(bus, "isa-parallel");
isadev = isa_new("isa-parallel");
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "index", index);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
isa_realize_and_unref(isadev, bus, &error_fatal);
}
void parallel_hds_isa_init(ISABus *bus, int n)

9
hw/char/serial-isa.c
View File

@ -75,7 +75,7 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
index++;
isa_init_irq(isadev, &s->irq, isa->isairq);
object_property_set_bool(OBJECT(s), true, "realized", errp);
qdev_realize(DEVICE(s), NULL, errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
@ -136,8 +136,7 @@ static void serial_isa_initfn(Object *o)
{
ISASerialState *self = ISA_SERIAL(o);
object_initialize_child(o, "serial", &self->state, sizeof(self->state),
TYPE_SERIAL, &error_abort, NULL);
object_initialize_child(o, "serial", &self->state, TYPE_SERIAL);
}
static const TypeInfo serial_isa_info = {
@ -160,11 +159,11 @@ static void serial_isa_init(ISABus *bus, int index, Chardev *chr)
DeviceState *dev;
ISADevice *isadev;
isadev = isa_create(bus, TYPE_ISA_SERIAL);
isadev = isa_new(TYPE_ISA_SERIAL);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "index", index);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_init_nofail(dev);
isa_realize_and_unref(isadev, bus, &error_fatal);
}
void serial_hds_isa_init(ISABus *bus, int from, int to)

8
hw/char/serial-pci-multi.c
View File

@ -56,7 +56,7 @@ static void multi_serial_pci_exit(PCIDevice *dev)
for (i = 0; i < pci->ports; i++) {
s = pci->state + i;
object_property_set_bool(OBJECT(s), false, "realized", &error_abort);
qdev_unrealize(DEVICE(s));
memory_region_del_subregion(&pci->iobar, &s->io);
g_free(pci->name[i]);
}
@ -106,7 +106,7 @@ static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
for (i = 0; i < nports; i++) {
s = pci->state + i;
object_property_set_bool(OBJECT(s), true, "realized", &err);
qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
multi_serial_pci_exit(dev);
@ -187,9 +187,7 @@ static void multi_serial_init(Object *o)
size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));
for (i = 0; i < nports; i++) {
object_initialize_child(o, "serial[*]", &pms->state[i],
sizeof(pms->state[i]),
TYPE_SERIAL, &error_abort, NULL);
object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL);
}
}

7
hw/char/serial-pci.c
View File

@ -49,7 +49,7 @@ static void serial_pci_realize(PCIDevice *dev, Error **errp)
SerialState *s = &pci->state;
Error *err = NULL;
object_property_set_bool(OBJECT(s), true, "realized", &err);
qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -68,7 +68,7 @@ static void serial_pci_exit(PCIDevice *dev)
PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
SerialState *s = &pci->state;
object_property_set_bool(OBJECT(s), false, "realized", &error_abort);
qdev_unrealize(DEVICE(s));
qemu_free_irq(s->irq);
}
@ -108,8 +108,7 @@ static void serial_pci_init(Object *o)
{
PCISerialState *ps = PCI_SERIAL(o);
object_initialize_child(o, "serial", &ps->state, sizeof(ps->state),
TYPE_SERIAL, &error_abort, NULL);
object_initialize_child(o, "serial", &ps->state, TYPE_SERIAL);
}
static const TypeInfo serial_pci_info = {

14
hw/char/serial.c
View File

@ -991,7 +991,7 @@ static void serial_io_realize(DeviceState *dev, Error **errp)
SerialState *s = &sio->serial;
Error *local_err = NULL;
object_property_set_bool(OBJECT(s), true, "realized", &local_err);
qdev_realize(DEVICE(s), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@ -1014,8 +1014,7 @@ static void serial_io_instance_init(Object *o)
{
SerialIO *sio = SERIAL_IO(o);
object_initialize_child(o, "serial", &sio->serial, sizeof(sio->serial),
TYPE_SERIAL, &error_abort, NULL);
object_initialize_child(o, "serial", &sio->serial, TYPE_SERIAL);
qdev_alias_all_properties(DEVICE(&sio->serial), o);
}
@ -1099,7 +1098,7 @@ static void serial_mm_realize(DeviceState *dev, Error **errp)
SerialState *s = &smm->serial;
Error *local_err = NULL;
object_property_set_bool(OBJECT(s), true, "realized", &local_err);
qdev_realize(DEVICE(s), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@ -1127,7 +1126,7 @@ SerialMM *serial_mm_init(MemoryRegion *address_space,
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end)
{
SerialMM *smm = SERIAL_MM(qdev_create(NULL, TYPE_SERIAL_MM));
SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM));
MemoryRegion *mr;
qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift);
@ -1135,7 +1134,7 @@ SerialMM *serial_mm_init(MemoryRegion *address_space,
qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
qdev_init_nofail(DEVICE(smm));
sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
@ -1148,8 +1147,7 @@ static void serial_mm_instance_init(Object *o)
{
SerialMM *smm = SERIAL_MM(o);
object_initialize_child(o, "serial", &smm->serial, sizeof(smm->serial),
TYPE_SERIAL, &error_abort, NULL);
object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL);
qdev_alias_all_properties(DEVICE(&smm->serial), o);
}

4
hw/char/spapr_vty.c
View File

@ -158,9 +158,9 @@ void spapr_vty_create(SpaprVioBus *bus, Chardev *chardev)
{
DeviceState *dev;
dev = qdev_create(&bus->bus, "spapr-vty");
dev = qdev_new("spapr-vty");
qdev_prop_set_chr(dev, "chardev", chardev);
qdev_init_nofail(dev);
qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
}
static Property spapr_vty_properties[] = {

23
hw/core/bus.c
View File

@ -95,7 +95,7 @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
}
}
static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
{
const char *typename = object_get_typename(OBJECT(bus));
BusClass *bc;
@ -151,7 +151,7 @@ void qbus_create_inplace(void *bus, size_t size, const char *typename,
DeviceState *parent, const char *name)
{
object_initialize(bus, size, typename);
qbus_realize(bus, parent, name);
qbus_init(bus, parent, name);
}
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
@ -159,11 +159,25 @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam
BusState *bus;
bus = BUS(object_new(typename));
qbus_realize(bus, parent, name);
qbus_init(bus, parent, name);
return bus;
}
bool qbus_realize(BusState *bus, Error **errp)
{
Error *err = NULL;
object_property_set_bool(OBJECT(bus), true, "realized", &err);
error_propagate(errp, err);
return !err;
}
void qbus_unrealize(BusState *bus)
{
object_property_set_bool(OBJECT(bus), false, "realized", &error_abort);
}
static bool bus_get_realized(Object *obj, Error **errp)
{
BusState *bus = BUS(obj);
@ -186,8 +200,7 @@ static void bus_set_realized(Object *obj, bool value, Error **errp)
} else if (!value && bus->realized) {
QTAILQ_FOREACH(kid, &bus->children, sibling) {
DeviceState *dev = kid->child;
object_property_set_bool(OBJECT(dev), false, "realized",
&error_abort);
qdev_unrealize(dev);
}
if (bc->unrealize) {
bc->unrealize(bus);

2
hw/core/cpu.c
View File

@ -59,7 +59,7 @@ CPUState *cpu_create(const char *typename)
{
Error *err = NULL;
CPUState *cpu = CPU(object_new(typename));
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
qdev_realize(DEVICE(cpu), NULL, &err);
if (err != NULL) {
error_report_err(err);
object_unref(OBJECT(cpu));

147
hw/core/qdev.c
View File

@ -97,6 +97,9 @@ static void bus_add_child(BusState *bus, DeviceState *child)
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
{
BusState *old_parent_bus = dev->parent_bus;
DeviceClass *dc = DEVICE_GET_CLASS(dev);
assert(dc->bus_type && object_dynamic_cast(OBJECT(bus), dc->bus_type));
if (old_parent_bus) {
trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
@ -125,52 +128,30 @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
}
}
/* Create a new device. This only initializes the device state
structure and allows properties to be set. The device still needs
to be realized. See qdev-core.h. */
DeviceState *qdev_create(BusState *bus, const char *name)
/*
* Create a device on the heap.
* A type @name must exist.
* This only initializes the device state structure and allows
* properties to be set. The device still needs to be realized. See
* qdev-core.h.
*/
DeviceState *qdev_new(const char *name)
{
DeviceState *dev;
dev = qdev_try_create(bus, name);
if (!dev) {
if (bus) {
error_report("Unknown device '%s' for bus '%s'", name,
object_get_typename(OBJECT(bus)));
} else {
error_report("Unknown device '%s' for default sysbus", name);
}
abort();
}
return dev;
return DEVICE(object_new(name));
}
DeviceState *qdev_try_create(BusState *bus, const char *type)
/*
* Try to create a device on the heap.
* This is like qdev_new(), except it returns %NULL when type @name
* does not exist.
*/
DeviceState *qdev_try_new(const char *name)
{
DeviceState *dev;
if (object_class_by_name(type) == NULL) {
return NULL;
}
dev = DEVICE(object_new(type));
if (!dev) {
if (!object_class_by_name(name)) {
return NULL;
}
if (!bus) {
/* Assert that the device really is a SysBusDevice before
* we put it onto the sysbus. Non-sysbus devices which aren't
* being put onto a bus should be created with object_new(TYPE_FOO),
* not qdev_create(NULL, TYPE_FOO).
*/
g_assert(object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE));
bus = sysbus_get_default();
}
qdev_set_parent_bus(dev, bus);
object_unref(OBJECT(dev));
return dev;
return DEVICE(object_new(name));
}
static QTAILQ_HEAD(, DeviceListener) device_listeners
@ -392,36 +373,71 @@ static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb,
void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
qdev_unrealize(dev);
}
/*
* Realize @dev.
* Device properties should be set before calling this function. IRQs
* and MMIO regions should be connected/mapped after calling this
* function.
* On failure, report an error with error_report() and terminate the
* program. This is okay during machine creation. Don't use for
* hotplug, because there callers need to recover from failure.
* Exception: if you know the device's init() callback can't fail,
* then qdev_init_nofail() can't fail either, and is therefore usable
* even then. But relying on the device implementation that way is
* somewhat unclean, and best avoided.
* @dev must not be plugged into a bus.
* If @bus, plug @dev into @bus. This takes a reference to @dev.
* If @dev has no QOM parent, make one up, taking another reference.
* On success, return true.
* On failure, store an error through @errp and return false.
*/
void qdev_init_nofail(DeviceState *dev)
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
{
Error *err = NULL;
assert(!dev->realized);
assert(!dev->realized && !dev->parent_bus);
if (bus) {
qdev_set_parent_bus(dev, bus);
} else {
assert(!DEVICE_GET_CLASS(dev)->bus_type);
}
object_ref(OBJECT(dev));
object_property_set_bool(OBJECT(dev), true, "realized", &err);
if (err) {
error_reportf_err(err, "Initialization of device %s failed: ",
object_get_typename(OBJECT(dev)));
exit(1);
error_propagate(errp, err);
}
return !err;
}
/*
* Realize @dev and drop a reference.
* This is like qdev_realize(), except the caller must hold a
* (private) reference, which is dropped on return regardless of
* success or failure. Intended use:
* dev = qdev_new();
* [...]
* qdev_realize_and_unref(dev, bus, errp);
* Now @dev can go away without further ado.
*/
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
{
bool ret;
ret = qdev_realize(dev, bus, errp);
object_unref(OBJECT(dev));
return ret;
}
void qdev_unrealize(DeviceState *dev)
{
object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
}
static int qdev_assert_realized_properly(Object *obj, void *opaque)
{
DeviceState *dev = DEVICE(object_dynamic_cast(obj, TYPE_DEVICE));
DeviceClass *dc;
if (dev) {
dc = DEVICE_GET_CLASS(dev);
assert(dev->realized);
assert(dev->parent_bus || !dc->bus_type);
}
return 0;
}
void qdev_machine_creation_done(void)
@ -431,6 +447,9 @@ void qdev_machine_creation_done(void)
* only create hotpluggable devices
*/
qdev_hotplug = true;
object_child_foreach_recursive(object_get_root(),
qdev_assert_realized_properly, NULL);
}
bool qdev_machine_modified(void)
@ -919,9 +938,7 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
resettable_state_clear(&dev->reset);
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
object_property_set_bool(OBJECT(bus), true, "realized",
&local_err);
if (local_err != NULL) {
if (!qbus_realize(bus, errp)) {
goto child_realize_fail;
}
}
@ -946,8 +963,7 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
} else if (!value && dev->realized) {
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
object_property_set_bool(OBJECT(bus), false, "realized",
&error_abort);
qbus_unrealize(bus);
}
if (qdev_get_vmsd(dev)) {
vmstate_unregister(VMSTATE_IF(dev), qdev_get_vmsd(dev), dev);
@ -965,8 +981,7 @@ static void device_set_realized(Object *obj, bool value, Error **errp)
child_realize_fail:
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
object_property_set_bool(OBJECT(bus), false, "realized",
&error_abort);
qbus_unrealize(bus);
}
if (qdev_get_vmsd(dev)) {
@ -983,6 +998,10 @@ post_realize_fail:
fail:
error_propagate(errp, local_err);
if (unattached_parent) {
/*
* Beware, this doesn't just revert
* object_property_add_child(), it also runs bus_remove()!
*/
object_unparent(OBJECT(dev));
unattached_count--;
}
@ -1078,7 +1097,7 @@ static void device_unparent(Object *obj)
BusState *bus;
if (dev->realized) {
object_property_set_bool(obj, false, "realized", &error_abort);
qdev_unrealize(dev);
}
while (dev->num_child_bus) {
bus = QLIST_FIRST(&dev->child_bus);

27
hw/core/sysbus.c
View File

@ -217,7 +217,7 @@ void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size)
* from being set to NULL to break the normal init/realize
* of some devices.
*/
static void sysbus_realize(DeviceState *dev, Error **errp)
static void sysbus_device_realize(DeviceState *dev, Error **errp)
{
}
@ -230,9 +230,9 @@ DeviceState *sysbus_create_varargs(const char *name,
qemu_irq irq;
int n;
dev = qdev_create(NULL, name);
dev = qdev_new(name);
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_realize_and_unref(s, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
@ -250,6 +250,16 @@ DeviceState *sysbus_create_varargs(const char *name,
return dev;
}
bool sysbus_realize(SysBusDevice *dev, Error **errp)
{
return qdev_realize(DEVICE(dev), sysbus_get_default(), errp);
}
bool sysbus_realize_and_unref(SysBusDevice *dev, Error **errp)
{
return qdev_realize_and_unref(DEVICE(dev), sysbus_get_default(), errp);
}
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = SYS_BUS_DEVICE(dev);
@ -301,7 +311,7 @@ MemoryRegion *sysbus_address_space(SysBusDevice *dev)
static void sysbus_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->realize = sysbus_realize;
k->realize = sysbus_device_realize;
k->bus_type = TYPE_SYSTEM_BUS;
/*
* device_add plugs devices into a suitable bus. For "real" buses,
@ -325,7 +335,6 @@ static const TypeInfo sysbus_device_type_info = {
.class_init = sysbus_device_class_init,
};
/* This is a nasty hack to allow passing a NULL bus to qdev_create. */
static BusState *main_system_bus;
static void main_system_bus_create(void)
@ -346,14 +355,6 @@ BusState *sysbus_get_default(void)
return main_system_bus;
}
void sysbus_init_child_obj(Object *parent, const char *childname, void *child,
size_t childsize, const char *childtype)
{
object_initialize_child(parent, childname, child, childsize, childtype,
&error_abort, NULL);
qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
}
static void sysbus_register_types(void)
{
type_register_static(&system_bus_info);

5
hw/cpu/a15mpcore.c
View File

@ -42,8 +42,7 @@ static void a15mp_priv_initfn(Object *obj)
memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
sysbus_init_mmio(sbd, &s->container);
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
gic_class_name());
object_initialize_child(obj, "gic", &s->gic, gic_class_name());
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
}
@ -77,7 +76,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
}
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

23
hw/cpu/a9mpcore.c
View File

@ -32,18 +32,15 @@ static void a9mp_priv_initfn(Object *obj)
memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU);
object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU);
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer),
TYPE_A9_GTIMER);
object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER);
sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
TYPE_ARM_MPTIMER);
object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt),
TYPE_ARM_MPTIMER);
object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER);
}
static void a9mp_priv_realize(DeviceState *dev, Error **errp)
@ -60,7 +57,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -81,7 +78,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -96,7 +93,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
gtimerdev = DEVICE(&s->gtimer);
qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -105,7 +102,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
mptimerdev = DEVICE(&s->mptimer);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -114,7 +111,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
wdtdev = DEVICE(&s->wdt);
qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &err);
if (err != NULL) {
error_propagate(errp, err);
return;

18
hw/cpu/arm11mpcore.c
View File

@ -79,7 +79,7 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -91,7 +91,7 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -104,14 +104,14 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -129,17 +129,15 @@ static void mpcore_priv_initfn(Object *obj)
"mpcore-priv-container", 0x2000);
sysbus_init_mmio(sbd, &s->container);
sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
/* Request the legacy 11MPCore GIC behaviour: */
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
TYPE_ARM_MPTIMER);
object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
sysbus_init_child_obj(obj, "wdtimer", &s->wdtimer, sizeof(s->wdtimer),
TYPE_ARM_MPTIMER);
object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
}
static Property mpcore_priv_properties[] = {

10
hw/cpu/realview_mpcore.c
View File

@ -70,7 +70,7 @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp)
int i;
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->priv), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->priv), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -81,7 +81,7 @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp)
}
/* ??? IRQ routing is hardcoded to "normal" mode. */
for (n = 0; n < 4; n++) {
object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err);
sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -104,14 +104,12 @@ static void mpcore_rirq_init(Object *obj)
SysBusDevice *privbusdev;
int i;
sysbus_init_child_obj(obj, "a11priv", &s->priv, sizeof(s->priv),
TYPE_ARM11MPCORE_PRIV);
object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
privbusdev = SYS_BUS_DEVICE(&s->priv);
sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
for (i = 0; i < 4; i++) {
sysbus_init_child_obj(obj, "gic[*]", &s->gic[i], sizeof(s->gic[i]),
TYPE_REALVIEW_GIC);
object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC);
}
}

4
hw/cris/axis_dev88.c
View File

@ -289,9 +289,9 @@ void axisdev88_init(MachineState *machine)
&gpio_state.iomem);
dev = qdev_create(NULL, "etraxfs,pic");
qdev_init_nofail(dev);
dev = qdev_new("etraxfs,pic");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0x3001c000);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));

3
hw/display/ati.c
View File

@ -933,8 +933,9 @@ static void ati_vga_realize(PCIDevice *dev, Error **errp)
/* ddc, edid */
I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
bitbang_i2c_init(&s->bbi2c, i2cbus);
I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC));
i2c_set_slave_address(i2cddc, 0x50);
qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort);
/* mmio register space */
memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,

4
hw/display/milkymist-tmu2.c
View File

@ -543,8 +543,8 @@ DeviceState *milkymist_tmu2_create(hwaddr base, qemu_irq irq)
XFree(configs);
XCloseDisplay(d);
dev = qdev_create(NULL, TYPE_MILKYMIST_TMU2);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_MILKYMIST_TMU2);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

11
hw/display/sm501.c
View File

@ -1831,8 +1831,9 @@ static void sm501_init(SM501State *s, DeviceState *dev,
/* i2c */
s->i2c_bus = i2c_init_bus(dev, "sm501.i2c");
/* ddc */
I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC));
I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC));
i2c_set_slave_address(I2C_SLAVE(ddc), 0x50);
qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort);
/* mmio */
memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
@ -1967,16 +1968,16 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->state.mmio_region);
/* bridge to usb host emulation module */
usb_dev = qdev_create(NULL, "sysbus-ohci");
usb_dev = qdev_new("sysbus-ohci");
qdev_prop_set_uint32(usb_dev, "num-ports", 2);
qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
qdev_init_nofail(usb_dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
/* bridge to serial emulation module */
qdev_init_nofail(DEVICE(&s->serial));
sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0);
memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr);
/* TODO : chain irq to IRL */
@ -2022,7 +2023,7 @@ static void sm501_sysbus_init(Object *o)
SM501SysBusState *sm501 = SYSBUS_SM501(o);
SerialMM *smm = &sm501->serial;
sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM);
object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM);
qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);

3
hw/display/virtio-gpu-pci.c
View File

@ -33,9 +33,8 @@ static void virtio_gpu_pci_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
int i;
Error *local_error = NULL;
qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
object_property_set_bool(OBJECT(vdev), true, "realized", &local_error);
qdev_realize(vdev, BUS(&vpci_dev->bus), &local_error);
if (local_error) {
error_propagate(errp, local_error);

3
hw/display/virtio-vga.c
View File

@ -137,9 +137,8 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
vpci_dev->common.offset = offset;
/* init virtio bits */
qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
object_property_set_bool(OBJECT(g), true, "realized", &err);
qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), &err);
if (err) {
error_propagate(errp, err);
return;

13
hw/display/xlnx_dp.c
View File

@ -1244,15 +1244,15 @@ static void xlnx_dp_init(Object *obj)
/*
* Initialize AUX Bus.
*/
s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
s->aux_bus = aux_bus_init(DEVICE(obj), "aux");
/*
* Initialize DPCD and EDID..
*/
s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd"));
s->dpcd = DPCD(qdev_new("dpcd"));
object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd));
s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
s->edid = I2CDDC(qdev_new("i2c-ddc"));
i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid));
@ -1266,9 +1266,14 @@ static void xlnx_dp_realize(DeviceState *dev, Error **errp)
DisplaySurface *surface;
struct audsettings as;
qdev_init_nofail(DEVICE(s->dpcd));
aux_bus_realize(s->aux_bus);
qdev_realize(DEVICE(s->dpcd), BUS(s->aux_bus), &error_fatal);
aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000);
qdev_realize_and_unref(DEVICE(s->edid), BUS(aux_get_i2c_bus(s->aux_bus)),
&error_fatal);
s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
surface = qemu_console_surface(s->console);
xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,

9
hw/dma/i8257.c
View File

@ -27,6 +27,7 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/dma/i8257.h"
#include "qapi/error.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/log.h"
@ -638,21 +639,21 @@ void i8257_dma_init(ISABus *bus, bool high_page_enable)
ISADevice *isa1, *isa2;
DeviceState *d;
isa1 = isa_create(bus, TYPE_I8257);
isa1 = isa_new(TYPE_I8257);
d = DEVICE(isa1);
qdev_prop_set_int32(d, "base", 0x00);
qdev_prop_set_int32(d, "page-base", 0x80);
qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
qdev_prop_set_int32(d, "dshift", 0);
qdev_init_nofail(d);
isa_realize_and_unref(isa1, bus, &error_fatal);
isa2 = isa_create(bus, TYPE_I8257);
isa2 = isa_new(TYPE_I8257);
d = DEVICE(isa2);
qdev_prop_set_int32(d, "base", 0xc0);
qdev_prop_set_int32(d, "page-base", 0x88);
qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
qdev_prop_set_int32(d, "dshift", 1);
qdev_init_nofail(d);
isa_realize_and_unref(isa2, bus, &error_fatal);
isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2));
}

8
hw/dma/pxa2xx_dma.c
View File

@ -495,9 +495,9 @@ DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
dev = qdev_create(NULL, "pxa2xx-dma");
dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
@ -509,9 +509,9 @@ DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
dev = qdev_create(NULL, "pxa2xx-dma");
dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

5
hw/dma/rc4030.c
View File

@ -28,6 +28,7 @@
#include "hw/mips/mips.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
@ -744,8 +745,8 @@ DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_RC4030);
qdev_init_nofail(dev);
dev = qdev_new(TYPE_RC4030);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
*dmas = rc4030_allocate_dmas(dev, 4);
*dma_mr = &RC4030(dev)->dma_mr;

16
hw/dma/sparc32_dma.c
View File

@ -301,7 +301,7 @@ static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
SysBusESPState *sysbus;
ESPState *esp;
d = qdev_create(NULL, TYPE_ESP);
d = qdev_new(TYPE_ESP);
object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
sysbus = ESP_STATE(d);
esp = &sysbus->esp;
@ -310,7 +310,7 @@ static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2;
esp->dma_enabled = 1;
qdev_init_nofail(d);
sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
@ -343,11 +343,11 @@ static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
qemu_check_nic_model(nd, TYPE_LANCE);
d = qdev_create(NULL, TYPE_LANCE);
d = qdev_new(TYPE_LANCE);
object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
qdev_set_nic_properties(d, nd);
object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp);
qdev_init_nofail(d);
sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
@ -378,10 +378,10 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
return;
}
espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE);
object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma));
qdev_init_nofail(espdma);
sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp);
@ -393,10 +393,10 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->dmamem, 0x0,
sysbus_mmio_get_region(sbd, 0));
ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE);
object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma));
qdev_init_nofail(ledma);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance);

9
hw/dma/xilinx_axidma.c
View File

@ -579,13 +579,10 @@ static void xilinx_axidma_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
object_initialize_child(OBJECT(s), "axistream-connected-target",
&s->rx_data_dev, sizeof(s->rx_data_dev),
TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort,
NULL);
&s->rx_data_dev, TYPE_XILINX_AXI_DMA_DATA_STREAM);
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
&s->rx_control_dev, sizeof(s->rx_control_dev),
TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
NULL);
&s->rx_control_dev,
TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,

4
hw/hppa/dino.c
View File

@ -521,7 +521,7 @@ PCIBus *dino_init(MemoryRegion *addr_space,
PCIBus *b;
int i;
dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
s = DINO_PCI_HOST_BRIDGE(dev);
s->iar0 = s->iar1 = CPU_HPA + 3;
s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
@ -548,7 +548,7 @@ PCIBus *dino_init(MemoryRegion *addr_space,
&s->pci_mem, get_system_io(),
PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
s->parent_obj.bus = b;
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Set up windows into PCI bus memory. */
for (i = 1; i < 31; i++) {

4
hw/hppa/lasi.c
View File

@ -300,7 +300,7 @@ DeviceState *lasi_init(MemoryRegion *address_space)
DeviceState *dev;
LasiState *s;
dev = qdev_create(NULL, TYPE_LASI_CHIP);
dev = qdev_new(TYPE_LASI_CHIP);
s = LASI_CHIP(dev);
s->iar = CPU_HPA + 3;
@ -309,7 +309,7 @@ DeviceState *lasi_init(MemoryRegion *address_space)
s, "lasi", 0x100000);
memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
qdev_init_nofail(dev);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* LAN */
if (enable_lasi_lan()) {

4
hw/hppa/machine.c
View File

@ -124,9 +124,9 @@ static void machine_hppa_init(MachineState *machine)
/* Graphics setup. */
if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
dev = qdev_create(NULL, "artist");
qdev_init_nofail(dev);
dev = qdev_new("artist");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, LASI_GFX_HPA);
sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);
}

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