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Second RISC-V PR for QEMU 8.0

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* riscv_htif: Support console output via proxy syscall
 * Cleanup firmware and device tree loading
 * Fix elen check when using vector extensions
 * add RISC-V OpenSBI boot test
 * Ensure we always follow MISA parsing
 * Fix up masking of vsip/vsie accesses
 * Trap on writes to stimecmp from VS when hvictl.VTI=1
 * Introduce helper_set_rounding_mode_chkfrm
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Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging

Second RISC-V PR for QEMU 8.0

* riscv_htif: Support console output via proxy syscall
* Cleanup firmware and device tree loading
* Fix elen check when using vector extensions
* add RISC-V OpenSBI boot test
* Ensure we always follow MISA parsing
* Fix up masking of vsip/vsie accesses
* Trap on writes to stimecmp from VS when hvictl.VTI=1
* Introduce helper_set_rounding_mode_chkfrm

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# gpg: Signature made Fri 20 Jan 2023 07:38:37 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu: (37 commits)
  hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()
  target/riscv: Remove helper_set_rod_rounding_mode
  target/riscv: Introduce helper_set_rounding_mode_chkfrm
  tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
  target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
  target/riscv: Fix up masking of vsip/vsie accesses
  hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
  hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
  hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
  hw/riscv/sifive_u.c: simplify create_fdt()
  hw/riscv/virt.c: simplify create_fdt()
  hw/riscv/spike.c: simplify create_fdt()
  target/riscv: Use TARGET_FMT_lx for env->mhartid
  target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
  target/riscv/cpu: set cpu->cfg in register_cpu_props()
  hw/riscv/boot.c: use MachineState in riscv_load_kernel()
  hw/riscv/boot.c: use MachineState in riscv_load_initrd()
  hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
  hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
  hw/riscv/spike.c: load initrd right after riscv_load_kernel()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-20 16:17:56 +00:00
commit 65cc5ccf06
24 changed files with 716 additions and 539 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

172
hw/char/riscv_htif.c
View File

@ -38,21 +38,31 @@
} \
} while (0)
#define HTIF_DEV_SHIFT 56
#define HTIF_CMD_SHIFT 48
#define HTIF_DEV_SYSTEM 0
#define HTIF_DEV_CONSOLE 1
#define HTIF_SYSTEM_CMD_SYSCALL 0
#define HTIF_CONSOLE_CMD_GETC 0
#define HTIF_CONSOLE_CMD_PUTC 1
/* PK system call number */
#define PK_SYS_WRITE 64
static uint64_t fromhost_addr, tohost_addr;
static int address_symbol_set;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size)
{
if (strcmp("fromhost", st_name) == 0) {
address_symbol_set |= 1;
fromhost_addr = st_value;
if (st_size != 8) {
error_report("HTIF fromhost must be 8 bytes");
exit(1);
}
} else if (strcmp("tohost", st_name) == 0) {
address_symbol_set |= 2;
tohost_addr = st_value;
if (st_size != 8) {
error_report("HTIF tohost must be 8 bytes");
@ -75,20 +85,22 @@ static int htif_can_recv(void *opaque)
*/
static void htif_recv(void *opaque, const uint8_t *buf, int size)
{
HTIFState *htifstate = opaque;
HTIFState *s = opaque;
if (size != 1) {
return;
}
/* TODO - we need to check whether mfromhost is zero which indicates
the device is ready to receive. The current implementation
will drop characters */
/*
* TODO - we need to check whether mfromhost is zero which indicates
* the device is ready to receive. The current implementation
* will drop characters
*/
uint64_t val_written = htifstate->pending_read;
uint64_t val_written = s->pending_read;
uint64_t resp = 0x100 | *buf;
htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
}
/*
@ -110,10 +122,30 @@ static int htif_be_change(void *opaque)
return 0;
}
static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
/*
* See below the tohost register format.
*
* Bits 63:56 indicate the "device".
* Bits 55:48 indicate the "command".
*
* Device 0 is the syscall device, which is used to emulate Unixy syscalls.
* It only implements command 0, which has two subfunctions:
* - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
* describing the syscall.
* - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
* value indicating success and other values indicating failure.
*
* Device 1 is the blocking character device.
* - Command 0 reads a character
* - Command 1 writes a character from the 8 LSBs of tohost
*
* For RV32, the tohost register is zero-extended, so only device=0 and
* command=0 (i.e. HTIF syscalls/exit codes) are supported.
*/
static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
{
uint8_t device = val_written >> 56;
uint8_t cmd = val_written >> 48;
uint8_t device = val_written >> HTIF_DEV_SHIFT;
uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
int resp = 0;
@ -125,28 +157,40 @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
* 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
* 1: Console
*/
if (unlikely(device == 0x0)) {
if (unlikely(device == HTIF_DEV_SYSTEM)) {
/* frontend syscall handler, shutdown and exit code support */
if (cmd == 0x0) {
if (cmd == HTIF_SYSTEM_CMD_SYSCALL) {
if (payload & 0x1) {
/* exit code */
int exit_code = payload >> 1;
exit(exit_code);
} else {
qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
uint64_t syscall[8];
cpu_physical_memory_read(payload, syscall, sizeof(syscall));
if (syscall[0] == PK_SYS_WRITE &&
syscall[1] == HTIF_DEV_CONSOLE &&
syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
uint8_t ch;
cpu_physical_memory_read(syscall[2], &ch, 1);
qemu_chr_fe_write(&s->chr, &ch, 1);
resp = 0x100 | (uint8_t)payload;
} else {
qemu_log_mask(LOG_UNIMP,
"pk syscall proxy not supported\n");
}
}
} else {
qemu_log("HTIF device %d: unknown command\n", device);
}
} else if (likely(device == 0x1)) {
} else if (likely(device == HTIF_DEV_CONSOLE)) {
/* HTIF Console */
if (cmd == 0x0) {
if (cmd == HTIF_CONSOLE_CMD_GETC) {
/* this should be a queue, but not yet implemented as such */
htifstate->pending_read = val_written;
htifstate->env->mtohost = 0; /* clear to indicate we read */
s->pending_read = val_written;
s->tohost = 0; /* clear to indicate we read */
return;
} else if (cmd == 0x1) {
qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
} else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
resp = 0x100 | (uint8_t)payload;
} else {
qemu_log("HTIF device %d: unknown command\n", device);
@ -157,36 +201,36 @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
" payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
}
/*
* - latest bbl does not set fromhost to 0 if there is a value in tohost
* - with this code enabled, qemu hangs waiting for fromhost to go to 0
* - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
* - HTIF needs protocol documentation and a more complete state machine
while (!htifstate->fromhost_inprogress &&
htifstate->env->mfromhost != 0x0) {
}
*/
htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
htifstate->env->mtohost = 0; /* clear to indicate we read */
* Latest bbl does not set fromhost to 0 if there is a value in tohost.
* With this code enabled, qemu hangs waiting for fromhost to go to 0.
* With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
* HTIF needs protocol documentation and a more complete state machine.
*
* while (!s->fromhost_inprogress &&
* s->fromhost != 0x0) {
* }
*/
s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
s->tohost = 0; /* clear to indicate we read */
}
#define TOHOST_OFFSET1 (htifstate->tohost_offset)
#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
#define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
#define TOHOST_OFFSET1 (s->tohost_offset)
#define TOHOST_OFFSET2 (s->tohost_offset + 4)
#define FROMHOST_OFFSET1 (s->fromhost_offset)
#define FROMHOST_OFFSET2 (s->fromhost_offset + 4)
/* CPU wants to read an HTIF register */
static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
{
HTIFState *htifstate = opaque;
HTIFState *s = opaque;
if (addr == TOHOST_OFFSET1) {
return htifstate->env->mtohost & 0xFFFFFFFF;
return s->tohost & 0xFFFFFFFF;
} else if (addr == TOHOST_OFFSET2) {
return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
return (s->tohost >> 32) & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET1) {
return htifstate->env->mfromhost & 0xFFFFFFFF;
return s->fromhost & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET2) {
return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
return (s->fromhost >> 32) & 0xFFFFFFFF;
} else {
qemu_log("Invalid htif read: address %016" PRIx64 "\n",
(uint64_t)addr);
@ -196,27 +240,27 @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
/* CPU wrote to an HTIF register */
static void htif_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
uint64_t value, unsigned size)
{
HTIFState *htifstate = opaque;
HTIFState *s = opaque;
if (addr == TOHOST_OFFSET1) {
if (htifstate->env->mtohost == 0x0) {
htifstate->allow_tohost = 1;
htifstate->env->mtohost = value & 0xFFFFFFFF;
if (s->tohost == 0x0) {
s->allow_tohost = 1;
s->tohost = value & 0xFFFFFFFF;
} else {
htifstate->allow_tohost = 0;
s->allow_tohost = 0;
}
} else if (addr == TOHOST_OFFSET2) {
if (htifstate->allow_tohost) {
htifstate->env->mtohost |= value << 32;
htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
if (s->allow_tohost) {
s->tohost |= value << 32;
htif_handle_tohost_write(s, s->tohost);
}
} else if (addr == FROMHOST_OFFSET1) {
htifstate->fromhost_inprogress = 1;
htifstate->env->mfromhost = value & 0xFFFFFFFF;
s->fromhost_inprogress = 1;
s->fromhost = value & 0xFFFFFFFF;
} else if (addr == FROMHOST_OFFSET2) {
htifstate->env->mfromhost |= value << 32;
htifstate->fromhost_inprogress = 0;
s->fromhost |= value << 32;
s->fromhost_inprogress = 0;
} else {
qemu_log("Invalid htif write: address %016" PRIx64 "\n",
(uint64_t)addr);
@ -228,19 +272,19 @@ static const MemoryRegionOps htif_mm_ops = {
.write = htif_mm_write,
};
bool htif_uses_elf_symbols(void)
{
return (address_symbol_set == 3) ? true : false;
}
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
uint64_t nonelf_base, bool custom_base)
{
uint64_t base, size, tohost_offset, fromhost_offset;
if (!htif_uses_elf_symbols()) {
if (custom_base) {
fromhost_addr = nonelf_base;
tohost_addr = nonelf_base + 8;
} else {
if (!fromhost_addr || !tohost_addr) {
error_report("Invalid HTIF fromhost or tohost address");
exit(1);
}
}
base = MIN(tohost_addr, fromhost_addr);
@ -249,10 +293,6 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
fromhost_offset = fromhost_addr - base;
HTIFState *s = g_new0(HTIFState, 1);
s->address_space = address_space;
s->main_mem = main_mem;
s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
s->env = env;
s->tohost_offset = tohost_offset;
s->fromhost_offset = fromhost_offset;
s->pending_read = 0;

113
hw/riscv/boot.c
View File

@ -75,25 +75,67 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
}
}
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb)
const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
{
char *firmware_filename = NULL;
target_ulong firmware_end_addr = firmware_load_addr;
if (riscv_is_32bit(harts)) {
return RISCV32_BIOS_BIN;
}
if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
return RISCV64_BIOS_BIN;
}
static char *riscv_find_bios(const char *bios_filename)
{
char *filename;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename);
if (filename == NULL) {
if (!qtest_enabled()) {
/*
* We only ship OpenSBI binary bios images in the QEMU source.
* For machines that use images other than the default bios,
* running QEMU test will complain hence let's suppress the error
* report for QEMU testing.
*/
error_report("Unable to find the RISC-V BIOS \"%s\"",
bios_filename);
exit(1);
}
}
return filename;
}
char *riscv_find_firmware(const char *firmware_filename,
const char *default_machine_firmware)
{
char *filename = NULL;
if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) {
/*
* The user didn't specify -bios, or has specified "-bios default".
* That means we are going to load the OpenSBI binary included in
* the QEMU source.
*/
firmware_filename = riscv_find_firmware(default_machine_firmware);
} else if (strcmp(machine->firmware, "none")) {
firmware_filename = riscv_find_firmware(machine->firmware);
filename = riscv_find_bios(default_machine_firmware);
} else if (strcmp(firmware_filename, "none")) {
filename = riscv_find_bios(firmware_filename);
}
return filename;
}
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb)
{
char *firmware_filename;
target_ulong firmware_end_addr = firmware_load_addr;
firmware_filename = riscv_find_firmware(machine->firmware,
default_machine_firmware);
if (firmware_filename) {
/* If not "none" load the firmware */
firmware_end_addr = riscv_load_firmware(firmware_filename,
@ -104,28 +146,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
return firmware_end_addr;
}
char *riscv_find_firmware(const char *firmware_filename)
{
char *filename;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
if (filename == NULL) {
if (!qtest_enabled()) {
/*
* We only ship OpenSBI binary bios images in the QEMU source.
* For machines that use images other than the default bios,
* running QEMU test will complain hence let's suppress the error
* report for QEMU testing.
*/
error_report("Unable to load the RISC-V firmware \"%s\"",
firmware_filename);
exit(1);
}
}
return filename;
}
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb)
@ -133,6 +153,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
uint64_t firmware_entry, firmware_end;
ssize_t firmware_size;
g_assert(firmware_filename != NULL);
if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
&firmware_entry, NULL, &firmware_end, NULL,
0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
@ -151,12 +173,15 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1);
}
target_ulong riscv_load_kernel(const char *kernel_filename,
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong kernel_start_addr,
symbol_fn_t sym_cb)
{
const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry;
g_assert(kernel_filename != NULL);
/*
* NB: Use low address not ELF entry point to ensure that the fw_dynamic
* behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
@ -184,11 +209,16 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
exit(1);
}
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start)
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
{
const char *filename = machine->initrd_filename;
uint64_t mem_size = machine->ram_size;
void *fdt = machine->fdt;
hwaddr start, end;
ssize_t size;
g_assert(filename != NULL);
/*
* We want to put the initrd far enough into RAM that when the
* kernel is uncompressed it will not clobber the initrd. However
@ -200,18 +230,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
* halfway into RAM, and for boards with 256MB of RAM or more we put
* the initrd at 128MB.
*/
*start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
size = load_ramdisk(filename, *start, mem_size - *start);
size = load_ramdisk(filename, start, mem_size - start);
if (size == -1) {
size = load_image_targphys(filename, *start, mem_size - *start);
size = load_image_targphys(filename, start, mem_size - start);
if (size == -1) {
error_report("could not load ramdisk '%s'", filename);
exit(1);
}
}
return *start + size;
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
if (fdt) {
end = start + size;
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
}
}
uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)

12
hw/riscv/microchip_pfsoc.c
View File

@ -629,18 +629,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr, NULL);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-end", end);
riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {

14
hw/riscv/numa.c
View File

@ -156,15 +156,15 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
ms->numa_state->nodes[socket_id].node_mem : 0;
}
void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
const char *node_name, int socket_id)
void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
int socket_id)
{
if (numa_enabled(ms)) {
qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id);
}
}
void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
void riscv_socket_fdt_write_distance_matrix(const MachineState *ms)
{
int i, j, idx;
uint32_t *dist_matrix, dist_matrix_size;
@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
}
}
qemu_fdt_add_subnode(fdt, "/distance-map");
qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
qemu_fdt_add_subnode(ms->fdt, "/distance-map");
qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible",
"numa-distance-map-v1");
qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix",
dist_matrix, dist_matrix_size);
g_free(dist_matrix);
}

3
hw/riscv/opentitan.c
View File

@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename,
memmap[IBEX_DEV_RAM].base, NULL);
riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
}
}

3
hw/riscv/sifive_e.c
View File

@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename,
memmap[SIFIVE_E_DEV_DTIM].base, NULL);
riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
}
}

53
hw/riscv/sifive_u.c
View File

@ -94,11 +94,12 @@ static const MemMapEntry sifive_u_memmap[] = {
#define GEM_REVISION 0x10070109
static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
bool is_32_bit)
{
MachineState *ms = MACHINE(qdev_get_machine());
MachineState *ms = MACHINE(s);
uint64_t mem_size = ms->ram_size;
void *fdt;
int cpu;
int cpu, fdt_size;
uint32_t *cells;
char *nodename;
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
@ -112,14 +113,13 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
};
if (ms->dtb) {
fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
if (!fdt) {
error_report("load_device_tree() failed");
exit(1);
}
goto update_bootargs;
} else {
fdt = s->fdt = create_device_tree(&s->fdt_size);
fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@ -510,11 +510,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
g_free(nodename);
update_bootargs:
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
}
static void sifive_u_machine_reset(void *opaque, int n, int level)
@ -533,6 +528,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@ -565,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine)
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc.u_cpus));
create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
if (s->start_in_flash) {
/*
@ -595,30 +590,23 @@ static void sifive_u_machine_init(MachineState *machine)
break;
}
if (riscv_is_32bit(&s->soc.u_cpus)) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_BIN, start_addr, NULL);
}
firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
start_addr, NULL);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr, NULL);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
machine->kernel_cmdline);
}
} else {
/*
@ -630,14 +618,11 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
machine->ram_size, machine->fdt);
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
/* Set machine->fdt for 'dumpdtb' QMP/HMP command */
machine->fdt = s->fdt;
/* reset vector */
uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */

108
hw/riscv/spike.c
View File

@ -49,9 +49,10 @@ static const MemMapEntry spike_memmap[] = {
};
static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
bool is_32_bit, bool htif_custom_base)
{
void *fdt;
int fdt_size;
uint64_t addr, size;
unsigned long clint_addr;
int cpu, socket;
@ -64,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
"sifive,clint0", "riscv,clint0"
};
fdt = s->fdt = create_device_tree(&s->fdt_size);
fdt = mc->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@ -77,7 +78,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/htif");
qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
if (!htif_uses_elf_symbols()) {
if (htif_custom_base) {
qemu_fdt_setprop_cells(fdt, "/htif", "reg",
0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
}
@ -120,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
riscv_socket_fdt_write_id(mc, cpu_name, socket);
qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@ -153,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cells(fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
riscv_socket_fdt_write_id(mc, mem_name, socket);
g_free(mem_name);
clint_addr = memmap[SPIKE_CLINT].base +
@ -166,20 +167,29 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
riscv_socket_fdt_write_id(mc, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
g_free(clust_name);
}
riscv_socket_fdt_write_distance_matrix(mc, fdt);
riscv_socket_fdt_write_distance_matrix(mc);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
}
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
static bool spike_test_elf_image(char *filename)
{
Error *err = NULL;
load_elf_hdr(filename, NULL, NULL, &err);
if (err) {
error_free(err);
return false;
} else {
return true;
}
}
@ -189,11 +199,14 @@ static void spike_board_init(MachineState *machine)
SpikeState *s = SPIKE_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
target_ulong firmware_end_addr, kernel_start_addr;
target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
target_ulong kernel_start_addr;
char *firmware_name;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
char *soc_name;
int i, base_hartid, hart_count;
bool htif_custom_base = false;
/* Check socket count limit */
if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@ -255,29 +268,54 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
mask_rom);
/* Find firmware */
firmware_name = riscv_find_firmware(machine->firmware,
riscv_default_firmware_name(&s->soc[0]));
/*
* Not like other RISC-V machines that use plain binary bios images,
* keeping ELF files here was intentional because BIN files don't work
* for the Spike machine as HTIF emulation depends on ELF parsing.
* Test the given firmware or kernel file to see if it is an ELF image.
* If it is an ELF, we assume it contains the symbols required for
* the HTIF console, otherwise we fall back to use the custom base
* passed from device tree for the HTIF console.
*/
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
if (!firmware_name && !machine->kernel_filename) {
htif_custom_base = true;
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
if (firmware_name) {
htif_custom_base = !spike_test_elf_image(firmware_name);
}
if (!htif_custom_base && machine->kernel_filename) {
htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
}
}
/* Load firmware */
if (firmware_name) {
firmware_end_addr = riscv_load_firmware(firmware_name,
memmap[SPIKE_DRAM].base,
htif_symbol_callback);
g_free(firmware_name);
}
/* Create device tree */
create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
/* Load kernel */
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr,
kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
htif_symbol_callback);
if (machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
machine->kernel_cmdline);
}
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
@ -286,28 +324,9 @@ static void spike_board_init(MachineState *machine)
kernel_entry = 0;
}
/* Create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
/* Load initrd */
if (machine->kernel_filename && machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt);
/* Set machine->fdt for 'dumpdtb' QMP/HMP command */
machine->fdt = s->fdt;
machine->ram_size, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
@ -316,9 +335,8 @@ static void spike_board_init(MachineState *machine)
fdt_load_addr);
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom,
&s->soc[0].harts[0].env, serial_hd(0),
memmap[SPIKE_HTIF].base);
htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
htif_custom_base);
}
static void spike_machine_instance_init(Object *obj)

86
hw/riscv/virt.c
View File

@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
char *clust_name, uint32_t *phandle,
bool is_32_bit, uint32_t *intc_phandles)
uint32_t *intc_phandles)
{
int cpu;
uint32_t cpu_phandle;
MachineState *mc = MACHINE(s);
char *name, *cpu_name, *core_name, *intc_name;
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
cpu_phandle = (*phandle)++;
@ -252,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
s->soc[socket].hartid_base + cpu);
qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
riscv_socket_fdt_write_id(mc, cpu_name, socket);
qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
intc_phandles[cpu] = (*phandle)++;
@ -290,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s,
qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
riscv_socket_fdt_write_id(mc, mem_name, socket);
g_free(mem_name);
}
@ -326,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
riscv_socket_fdt_write_id(mc, clint_name, socket);
g_free(clint_name);
g_free(clint_cells);
@ -371,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
aclint_mswi_cells, aclint_cells_size);
qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
riscv_socket_fdt_write_id(mc, name, socket);
g_free(name);
}
@ -395,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
0x0, RISCV_ACLINT_DEFAULT_MTIME);
qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
aclint_mtimer_cells, aclint_cells_size);
riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
riscv_socket_fdt_write_id(mc, name, socket);
g_free(name);
if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
@ -411,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
aclint_sswi_cells, aclint_cells_size);
qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
riscv_socket_fdt_write_id(mc, name, socket);
g_free(name);
}
@ -470,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
VIRT_IRQCHIP_NUM_SOURCES - 1);
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
riscv_socket_fdt_write_id(mc, plic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
@ -662,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
aplic_s_phandle);
qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
riscv_socket_fdt_write_id(mc, aplic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
g_free(aplic_name);
@ -690,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
riscv_socket_fdt_write_id(mc, aplic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
if (!socket) {
@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s)
}
static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *phandle,
uint32_t *irq_mmio_phandle,
uint32_t *irq_pcie_phandle,
uint32_t *irq_virtio_phandle,
@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(mc->fdt, clust_name);
create_fdt_socket_cpus(s, socket, clust_name, phandle,
is_32_bit, &intc_phandles[phandle_pos]);
&intc_phandles[phandle_pos]);
create_fdt_socket_memory(s, memmap, socket);
@ -804,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
}
}
riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
riscv_socket_fdt_write_distance_matrix(mc);
}
static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
g_free(nodename);
}
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
{
MachineState *mc = MACHINE(s);
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
error_report("load_device_tree() failed");
exit(1);
}
goto update_bootargs;
} else {
mc->fdt = create_device_tree(&s->fdt_size);
if (!mc->fdt) {
@ -1032,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
create_fdt_sockets(s, memmap, is_32_bit, &phandle,
&irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
&msi_pcie_phandle);
create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
&irq_pcie_phandle, &irq_virtio_phandle,
&msi_pcie_phandle);
create_fdt_virtio(s, memmap, irq_virtio_phandle);
@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_fw_cfg(s, memmap);
create_fdt_pmu(s);
update_bootargs:
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
/* Pass seed to RNG */
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
@ -1237,6 +1231,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
MachineState *machine = MACHINE(s);
target_ulong start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
uint32_t fdt_load_addr;
uint64_t kernel_entry;
@ -1256,20 +1251,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
}
}
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
RISCV64_BIOS_BIN, start_addr, NULL);
}
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
* tree cannot be altered and we get FDT_ERR_NOSPACE.
*/
s->fw_cfg = create_fw_cfg(machine);
rom_set_fw(s->fw_cfg);
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
start_addr, NULL);
if (drive_get(IF_PFLASH, 0, 1)) {
/*
@ -1291,18 +1274,15 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr, NULL);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
end);
riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
machine->kernel_cmdline);
}
} else {
/*
@ -1481,6 +1461,13 @@ static void virt_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
* device tree cannot be altered and we get FDT_ERR_NOSPACE.
*/
s->fw_cfg = create_fw_cfg(machine);
rom_set_fw(s->fw_cfg);
/* SiFive Test MMIO device */
sifive_test_create(memmap[VIRT_TEST].base);
@ -1520,8 +1507,7 @@ static void virt_machine_init(MachineState *machine)
virt_flash_map(s, system_memory);
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(&s->soc[0]));
create_fdt(s, memmap);
s->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&s->machine_done);

19
include/hw/char/riscv_htif.h
View File

@ -23,7 +23,6 @@
#include "chardev/char.h"
#include "chardev/char-fe.h"
#include "exec/memory.h"
#include "target/riscv/cpu.h"
#define TYPE_HTIF_UART "riscv.htif.uart"
@ -31,32 +30,22 @@ typedef struct HTIFState {
int allow_tohost;
int fromhost_inprogress;
uint64_t tohost;
uint64_t fromhost;
hwaddr tohost_offset;
hwaddr fromhost_offset;
uint64_t tohost_size;
uint64_t fromhost_size;
MemoryRegion mmio;
MemoryRegion *address_space;
MemoryRegion *main_mem;
void *main_mem_ram_ptr;
CPURISCVState *env;
CharBackend chr;
uint64_t pending_read;
} HTIFState;
extern const VMStateDescription vmstate_htif;
extern const MemoryRegionOps htif_io_ops;
/* HTIF symbol callback */
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size);
/* Check if HTIF uses ELF symbols */
bool htif_uses_elf_symbols(void);
/* legacy pre qom */
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
uint64_t nonelf_base, bool custom_base);
#endif

9
include/hw/riscv/boot.h
View File

@ -37,15 +37,16 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
char *riscv_find_firmware(const char *firmware_filename);
const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
char *riscv_find_firmware(const char *firmware_filename,
const char *default_machine_firmware);
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(const char *kernel_filename,
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,

10
include/hw/riscv/numa.h
View File

@ -90,19 +90,19 @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
* @ms: pointer to machine state
* @socket_id: socket index
*
* Write NUMA node-id FDT property for given FDT node
* Write NUMA node-id FDT property in MachineState->fdt
*/
void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
const char *node_name, int socket_id);
void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
int socket_id);
/**
* riscv_socket_fdt_write_distance_matrix:
* @ms: pointer to machine state
* @socket_id: socket index
*
* Write NUMA distance matrix in FDT for given machine
* Write NUMA distance matrix in MachineState->fdt
*/
void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
void riscv_socket_fdt_write_distance_matrix(const MachineState *ms);
CpuInstanceProperties
riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);

3
include/hw/riscv/sifive_u.h
View File

@ -69,9 +69,6 @@ typedef struct SiFiveUState {
/*< public >*/
SiFiveUSoCState soc;
void *fdt;
int fdt_size;
bool start_in_flash;
uint32_t msel;
uint32_t serial;

2
include/hw/riscv/spike.h
View File

@ -37,8 +37,6 @@ struct SpikeState {
/*< public >*/
RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
void *fdt;
int fdt_size;
};
enum {

445
target/riscv/cpu.c
View File

@ -256,6 +256,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@ -265,6 +266,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@ -299,6 +301,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@ -308,6 +311,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@ -318,6 +322,7 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
cpu->cfg.epmp = true;
@ -329,6 +334,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@ -619,6 +625,207 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly, doing a set_misa() in the end.
*/
static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
uint32_t ext = 0;
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
}
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
error_setg(errp,
"Either I or E extension must be set");
return;
}
if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
}
if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
error_setg(errp, "D extension requires F extension");
return;
}
if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
error_setg(errp, "V extension requires D extension");
return;
}
if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
cpu->cfg.ext_zhinxmin) {
cpu->cfg.ext_zfinx = true;
}
if (cpu->cfg.ext_zfinx) {
if (!cpu->cfg.ext_icsr) {
error_setg(errp, "Zfinx extension requires Zicsr");
return;
}
if (cpu->cfg.ext_f) {
error_setg(errp,
"Zfinx cannot be supported together with F extension");
return;
}
}
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
if (cpu->cfg.ext_zkn) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zkne = true;
cpu->cfg.ext_zknd = true;
cpu->cfg.ext_zknh = true;
}
if (cpu->cfg.ext_zks) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
if (cpu->cfg.ext_i) {
ext |= RVI;
}
if (cpu->cfg.ext_e) {
ext |= RVE;
}
if (cpu->cfg.ext_m) {
ext |= RVM;
}
if (cpu->cfg.ext_a) {
ext |= RVA;
}
if (cpu->cfg.ext_f) {
ext |= RVF;
}
if (cpu->cfg.ext_d) {
ext |= RVD;
}
if (cpu->cfg.ext_c) {
ext |= RVC;
}
if (cpu->cfg.ext_s) {
ext |= RVS;
}
if (cpu->cfg.ext_u) {
ext |= RVU;
}
if (cpu->cfg.ext_h) {
ext |= RVH;
}
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_1_00_0;
ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
"Vector extension VLEN must be power of 2");
return;
}
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
error_setg(errp,
"Vector extension implementation only supports VLEN "
"in the range [128, %d]", RV_VLEN_MAX);
return;
}
if (!is_power_of_2(cpu->cfg.elen)) {
error_setg(errp,
"Vector extension ELEN must be power of 2");
return;
}
if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
error_setg(errp,
"Vector extension implementation only supports ELEN "
"in the range [8, 64]");
return;
}
if (cpu->cfg.vext_spec) {
if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
cpu->cfg.vext_spec);
return;
}
} else {
qemu_log("vector version is not specified, "
"use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
}
set_misa(env, env->misa_mxl, ext);
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@ -660,9 +867,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
(env->priv_ver < isa_edata_arr[i].min_version)) {
isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x%lx because "
"privilege spec version does not match",
isa_edata_arr[i].name, (unsigned long)env->mhartid);
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
isa_edata_arr[i].name, env->mhartid);
#else
warn_report("disabling %s extension because "
"privilege spec version does not match",
@ -714,200 +921,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
assert(env->misa_mxl_max == env->misa_mxl);
/* If only MISA_EXT is unset for misa, then set it from properties */
if (env->misa_ext == 0) {
uint32_t ext = 0;
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
}
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
error_setg(errp,
"Either I or E extension must be set");
return;
}
if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
}
if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
}
if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
error_setg(errp, "D extension requires F extension");
return;
}
if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
error_setg(errp, "V extension requires D extension");
return;
}
if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
cpu->cfg.ext_zhinxmin) {
cpu->cfg.ext_zfinx = true;
}
if (cpu->cfg.ext_zfinx) {
if (!cpu->cfg.ext_icsr) {
error_setg(errp, "Zfinx extension requires Zicsr");
return;
}
if (cpu->cfg.ext_f) {
error_setg(errp,
"Zfinx cannot be supported together with F extension");
return;
}
}
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
if (cpu->cfg.ext_zkn) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zkne = true;
cpu->cfg.ext_zknd = true;
cpu->cfg.ext_zknh = true;
}
if (cpu->cfg.ext_zks) {
cpu->cfg.ext_zbkb = true;
cpu->cfg.ext_zbkc = true;
cpu->cfg.ext_zbkx = true;
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
if (cpu->cfg.ext_i) {
ext |= RVI;
}
if (cpu->cfg.ext_e) {
ext |= RVE;
}
if (cpu->cfg.ext_m) {
ext |= RVM;
}
if (cpu->cfg.ext_a) {
ext |= RVA;
}
if (cpu->cfg.ext_f) {
ext |= RVF;
}
if (cpu->cfg.ext_d) {
ext |= RVD;
}
if (cpu->cfg.ext_c) {
ext |= RVC;
}
if (cpu->cfg.ext_s) {
ext |= RVS;
}
if (cpu->cfg.ext_u) {
ext |= RVU;
}
if (cpu->cfg.ext_h) {
ext |= RVH;
}
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_1_00_0;
ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
"Vector extension VLEN must be power of 2");
return;
}
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
error_setg(errp,
"Vector extension implementation only supports VLEN "
"in the range [128, %d]", RV_VLEN_MAX);
return;
}
if (!is_power_of_2(cpu->cfg.elen)) {
error_setg(errp,
"Vector extension ELEN must be power of 2");
return;
}
if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
error_setg(errp,
"Vector extension implementation only supports ELEN "
"in the range [8, 64]");
return;
}
if (cpu->cfg.vext_spec) {
if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
cpu->cfg.vext_spec);
return;
}
} else {
qemu_log("vector version is not specified, "
"use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
}
set_misa(env, env->misa_mxl, ext);
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
#ifndef CONFIG_USER_ONLY
@ -1083,10 +1100,44 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
/*
* Register CPU props based on env.misa_ext. If a non-zero
* value was set, register only the required cpu->cfg.ext_*
* properties and leave. env.misa_ext = 0 means that we want
* all the default properties to be registered.
*/
static void register_cpu_props(DeviceState *dev)
{
RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
/*
* If misa_ext is not zero, set cfg properties now to
* allow them to be read during riscv_cpu_realize()
* later on.
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_a = misa_ext & RVA;
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_c = misa_ext & RVC;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
/*
* We don't want to set the default riscv_cpu_extensions
* in this case.
*/
return;
}
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
qdev_property_add_static(dev, prop);
}

8
target/riscv/cpu.h
View File

@ -63,6 +63,10 @@
#define RV(x) ((target_ulong)1 << (x - 'A'))
/*
* Consider updating register_cpu_props() when adding
* new MISA bits here.
*/
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
@ -309,10 +313,6 @@ struct CPUArchState {
target_ulong sscratch;
target_ulong mscratch;
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
/* Sstc CSRs */
uint64_t stimecmp;

39
target/riscv/csr.c
View File

@ -1037,6 +1037,9 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return write_vstimecmp(env, csrno, val);
}
@ -1057,6 +1060,9 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return write_vstimecmph(env, csrno, val);
}
@ -2305,22 +2311,15 @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
new_val &= ~(VS_MODE_INTERRUPTS >> 1);
new_val |= vsbits << 1;
vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
wr_mask |= vsbits << 1;
new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
if (ret_val) {
rval &= mask;
vsbits = rval & VS_MODE_INTERRUPTS;
rval &= ~VS_MODE_INTERRUPTS;
*ret_val = rval | (vsbits >> 1);
*ret_val = (rval & mask) >> 1;
}
return ret;
@ -2521,22 +2520,16 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
new_val &= ~(VS_MODE_INTERRUPTS >> 1);
new_val |= vsbits << 1;
vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
wr_mask |= vsbits << 1;
new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
ret = rmw_mip64(env, csrno, &rval, new_val,
wr_mask & mask & vsip_writable_mask);
if (ret_val) {
rval &= mask;
vsbits = rval & VS_MODE_INTERRUPTS;
rval &= ~VS_MODE_INTERRUPTS;
*ret_val = rval | (vsbits >> 1);
*ret_val = (rval & mask) >> 1;
}
return ret;

36
target/riscv/fpu_helper.c
View File

@ -81,9 +81,41 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
void helper_set_rod_rounding_mode(CPURISCVState *env)
void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
{
set_float_rounding_mode(float_round_to_odd, &env->fp_status);
int softrm;
/* Always validate frm, even if rm != DYN. */
if (unlikely(env->frm >= 5)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
if (rm == RISCV_FRM_DYN) {
rm = env->frm;
}
switch (rm) {
case RISCV_FRM_RNE:
softrm = float_round_nearest_even;
break;
case RISCV_FRM_RTZ:
softrm = float_round_to_zero;
break;
case RISCV_FRM_RDN:
softrm = float_round_down;
break;
case RISCV_FRM_RUP:
softrm = float_round_up;
break;
case RISCV_FRM_RMM:
softrm = float_round_ties_away;
break;
case RISCV_FRM_ROD:
softrm = float_round_to_odd;
break;
default:
g_assert_not_reached();
}
set_float_rounding_mode(softrm, &env->fp_status);
}
static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,

2
target/riscv/helper.h
View File

@ -3,7 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)

24
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
int rm)
{
if (checkfn(s, a)) {
if (rm != RISCV_FRM_DYN) {
gen_set_rm(s, RISCV_FRM_DYN);
}
uint32_t data = 0;
TCGLabel *over = gen_new_label();
gen_set_rm(s, rm);
gen_set_rm_chkfrm(s, rm);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (CHECK(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
gen_set_rm(s, FRM); \
gen_set_rm_chkfrm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (CHECK(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
gen_set_rm(s, FRM); \
gen_set_rm_chkfrm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opxfv_narrow_check(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##HELPER##_b, \
@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
gen_set_rm(s, FRM); \
gen_set_rm_chkfrm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\

6
target/riscv/machine.c
View File

@ -333,8 +333,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 5,
.minimum_version_id = 5,
.version_id = 6,
.minimum_version_id = 6,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@ -384,8 +384,6 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
VMSTATE_UINT64(env.mtohost, RISCVCPU),
VMSTATE_UINT64(env.stimecmp, RISCVCPU),
VMSTATE_END_OF_LIST()

21
target/riscv/translate.c
View File

@ -114,6 +114,8 @@ typedef struct DisasContext {
bool pm_base_enabled;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
bool frm_valid;
/* TCG of the current insn_start */
TCGOp *insn_start;
} DisasContext;
@ -670,9 +672,9 @@ static void gen_set_rm(DisasContext *ctx, int rm)
}
ctx->frm = rm;
if (rm == RISCV_FRM_ROD) {
gen_helper_set_rod_rounding_mode(cpu_env);
return;
if (rm == RISCV_FRM_DYN) {
/* The helper will return only if frm valid. */
ctx->frm_valid = true;
}
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
@ -680,6 +682,19 @@ static void gen_set_rm(DisasContext *ctx, int rm)
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
}
static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
{
if (ctx->frm == rm && ctx->frm_valid) {
return;
}
ctx->frm = rm;
ctx->frm_valid = true;
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
}
static int ex_plus_1(DisasContext *ctx, int nf)
{
return nf + 1;

2
tcg/riscv/tcg-target.c.inc
View File

@ -599,7 +599,7 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
intptr_t imm12 = sextreg(offset, 0, 12);
if (offset != imm12) {
intptr_t diff = offset - (uintptr_t)s->code_ptr;
intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
imm12 = sextreg(diff, 0, 12);

65
tests/avocado/riscv_opensbi.py Normal file
View File

@ -0,0 +1,65 @@
# OpenSBI boot test for RISC-V machines
#
# Copyright (c) 2022, Ventana Micro
#
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
from avocado_qemu import QemuSystemTest
from avocado import skip
from avocado_qemu import wait_for_console_pattern
class RiscvOpenSBI(QemuSystemTest):
"""
:avocado: tags=accel:tcg
"""
timeout = 5
def boot_opensbi(self):
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG')
@skip("requires OpenSBI fix to work")
def test_riscv32_spike(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:spike
"""
self.boot_opensbi()
def test_riscv64_spike(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:spike
"""
self.boot_opensbi()
def test_riscv32_sifive_u(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:sifive_u
"""
self.boot_opensbi()
def test_riscv64_sifive_u(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:sifive_u
"""
self.boot_opensbi()
def test_riscv32_virt(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:virt
"""
self.boot_opensbi()
def test_riscv64_virt(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:virt
"""
self.boot_opensbi()