tcg-s390: Cleanup argument shuffling fixme in softmmu code
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
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f0bffc2730
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65a62a753c
@ -393,6 +393,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set32(ct->u.regs, 0, 0xffff);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
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break;
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case 'a': /* force R2 for division */
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ct->ct |= TCG_CT_REG;
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@ -1436,27 +1437,29 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data,
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}
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#if defined(CONFIG_SOFTMMU)
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static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
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TCGReg addr_reg, int mem_index, int opc,
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uint16_t **label2_ptr_p, int is_store)
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static TCGReg tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
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TCGReg addr_reg, int mem_index, int opc,
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uint16_t **label2_ptr_p, int is_store)
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{
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const TCGReg arg0 = TCG_REG_R2;
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const TCGReg arg1 = TCG_REG_R3;
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const TCGReg arg0 = tcg_target_call_iarg_regs[0];
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const TCGReg arg1 = tcg_target_call_iarg_regs[1];
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const TCGReg arg2 = tcg_target_call_iarg_regs[2];
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const TCGReg arg3 = tcg_target_call_iarg_regs[3];
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int s_bits = opc & 3;
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uint16_t *label1_ptr;
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tcg_target_long ofs;
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if (TARGET_LONG_BITS == 32) {
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tgen_ext32u(s, arg0, addr_reg);
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tgen_ext32u(s, arg1, addr_reg);
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} else {
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tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
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tcg_out_mov(s, TCG_TYPE_I64, arg1, addr_reg);
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}
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tcg_out_sh64(s, RSY_SRLG, arg1, addr_reg, TCG_REG_NONE,
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tcg_out_sh64(s, RSY_SRLG, arg2, addr_reg, TCG_REG_NONE,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tgen_andi(s, TCG_TYPE_I64, arg0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
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tgen_andi(s, TCG_TYPE_I64, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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tgen_andi(s, TCG_TYPE_I64, arg1, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
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tgen_andi(s, TCG_TYPE_I64, arg2, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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if (is_store) {
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ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
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@ -1466,15 +1469,15 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
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assert(ofs < 0x80000);
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if (TARGET_LONG_BITS == 32) {
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tcg_out_mem(s, RX_C, RXY_CY, arg0, arg1, TCG_AREG0, ofs);
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tcg_out_mem(s, RX_C, RXY_CY, arg1, arg2, TCG_AREG0, ofs);
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} else {
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tcg_out_mem(s, 0, RXY_CG, arg0, arg1, TCG_AREG0, ofs);
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tcg_out_mem(s, 0, RXY_CG, arg1, arg2, TCG_AREG0, ofs);
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}
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if (TARGET_LONG_BITS == 32) {
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tgen_ext32u(s, arg0, addr_reg);
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tgen_ext32u(s, arg1, addr_reg);
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} else {
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tcg_out_mov(s, TCG_TYPE_I64, arg0, addr_reg);
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tcg_out_mov(s, TCG_TYPE_I64, arg1, addr_reg);
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}
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label1_ptr = (uint16_t*)s->code_ptr;
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@ -1488,56 +1491,42 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
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for the calling convention. */
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switch (opc) {
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case LD_UINT8:
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tgen_ext8u(s, TCG_TYPE_I64, arg1, data_reg);
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tgen_ext8u(s, TCG_TYPE_I64, arg2, data_reg);
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break;
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case LD_UINT16:
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tgen_ext16u(s, TCG_TYPE_I64, arg1, data_reg);
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tgen_ext16u(s, TCG_TYPE_I64, arg2, data_reg);
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break;
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case LD_UINT32:
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tgen_ext32u(s, arg1, data_reg);
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tgen_ext32u(s, arg2, data_reg);
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break;
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case LD_UINT64:
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tcg_out_mov(s, TCG_TYPE_I64, arg1, data_reg);
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tcg_out_mov(s, TCG_TYPE_I64, arg2, data_reg);
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break;
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default:
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tcg_abort();
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}
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
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/* XXX/FIXME: suboptimal */
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
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tcg_target_call_iarg_regs[2]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
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tcg_target_call_iarg_regs[1]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
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tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
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TCG_AREG0);
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tcg_out_movi(s, TCG_TYPE_I32, arg3, mem_index);
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tcg_out_mov(s, TCG_TYPE_I64, arg0, TCG_AREG0);
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tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
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} else {
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tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
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/* XXX/FIXME: suboptimal */
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
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tcg_target_call_iarg_regs[1]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
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tcg_target_call_iarg_regs[0]);
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tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
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TCG_AREG0);
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tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
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tcg_out_mov(s, TCG_TYPE_I64, arg0, TCG_AREG0);
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tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
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/* sign extension */
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switch (opc) {
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case LD_INT8:
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tgen_ext8s(s, TCG_TYPE_I64, data_reg, arg0);
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tgen_ext8s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
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break;
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case LD_INT16:
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tgen_ext16s(s, TCG_TYPE_I64, data_reg, arg0);
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tgen_ext16s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
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break;
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case LD_INT32:
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tgen_ext32s(s, data_reg, arg0);
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tgen_ext32s(s, data_reg, TCG_REG_R2);
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break;
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default:
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/* unsigned -> just copy */
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tcg_out_mov(s, TCG_TYPE_I64, data_reg, arg0);
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tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
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break;
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}
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}
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@ -1554,7 +1543,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
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ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
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assert(ofs < 0x80000);
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tcg_out_mem(s, 0, RXY_AG, arg0, arg1, TCG_AREG0, ofs);
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tcg_out_mem(s, 0, RXY_AG, arg1, arg2, TCG_AREG0, ofs);
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return arg1;
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}
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static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr)
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@ -1600,10 +1591,10 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
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#if defined(CONFIG_SOFTMMU)
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mem_index = *args;
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tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
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opc, &label2_ptr, 0);
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addr_reg = tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
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opc, &label2_ptr, 0);
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tcg_out_qemu_ld_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
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tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, TCG_REG_NONE, 0);
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tcg_finish_qemu_ldst(s, label2_ptr);
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#else
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@ -1629,10 +1620,10 @@ static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc)
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#if defined(CONFIG_SOFTMMU)
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mem_index = *args;
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tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
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opc, &label2_ptr, 1);
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addr_reg = tcg_prepare_qemu_ldst(s, data_reg, addr_reg, mem_index,
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opc, &label2_ptr, 1);
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tcg_out_qemu_st_direct(s, opc, data_reg, TCG_REG_R2, TCG_REG_NONE, 0);
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tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, TCG_REG_NONE, 0);
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tcg_finish_qemu_ldst(s, label2_ptr);
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#else
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