disas/nanomips: Remove __cond methods from class
NMD class methods with the conditional_function type like NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD class. They're now declared global static functions. Therefore, typedef of the function pointer, conditional_function is defined outside of the class. Now that conditional_function type functions are not part of the NMD class we can't access them using the this pointer. Thus, the use of the this pointer has been deleted. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-7-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -784,7 +784,7 @@ int NMD::Disassemble(const uint16 * data, std::string & dis,
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if ((op_code & table[i].mask) == table[i].value) {
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if ((op_code & table[i].mask) == table[i].value) {
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/* possible match */
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/* possible match */
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conditional_function cond = table[i].condition;
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conditional_function cond = table[i].condition;
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if ((cond == 0) || (this->*cond)(op_code)) {
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if ((cond == NULL) || cond(op_code)) {
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try
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try
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{
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{
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if (table[i].type == pool) {
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if (table[i].type == pool) {
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@ -1672,28 +1672,28 @@ static uint64 extract_u_3_2_1_0__s1(uint64 instruction)
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bool NMD::ADDIU_32__cond(uint64 instruction)
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static bool ADDIU_32__cond(uint64 instruction)
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{
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{
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uint64 rt = extract_rt_25_24_23_22_21(instruction);
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uint64 rt = extract_rt_25_24_23_22_21(instruction);
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return rt != 0;
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return rt != 0;
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}
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}
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bool NMD::ADDIU_RS5__cond(uint64 instruction)
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static bool ADDIU_RS5__cond(uint64 instruction)
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{
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{
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uint64 rt = extract_rt_9_8_7_6_5(instruction);
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uint64 rt = extract_rt_9_8_7_6_5(instruction);
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return rt != 0;
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return rt != 0;
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}
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}
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bool NMD::BALRSC_cond(uint64 instruction)
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static bool BALRSC_cond(uint64 instruction)
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{
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{
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uint64 rt = extract_rt_25_24_23_22_21(instruction);
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uint64 rt = extract_rt_25_24_23_22_21(instruction);
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return rt != 0;
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return rt != 0;
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}
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}
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bool NMD::BEQC_16__cond(uint64 instruction)
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static bool BEQC_16__cond(uint64 instruction)
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{
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{
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uint64 rs3 = extract_rs3_6_5_4(instruction);
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uint64 rs3 = extract_rs3_6_5_4(instruction);
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uint64 rt3 = extract_rt3_9_8_7(instruction);
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uint64 rt3 = extract_rt3_9_8_7(instruction);
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@ -1702,7 +1702,7 @@ bool NMD::BEQC_16__cond(uint64 instruction)
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}
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}
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bool NMD::BNEC_16__cond(uint64 instruction)
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static bool BNEC_16__cond(uint64 instruction)
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{
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{
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uint64 rs3 = extract_rs3_6_5_4(instruction);
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uint64 rs3 = extract_rs3_6_5_4(instruction);
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uint64 rt3 = extract_rt3_9_8_7(instruction);
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uint64 rt3 = extract_rt3_9_8_7(instruction);
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@ -1711,35 +1711,35 @@ bool NMD::BNEC_16__cond(uint64 instruction)
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}
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}
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bool NMD::MOVE_cond(uint64 instruction)
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static bool MOVE_cond(uint64 instruction)
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{
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{
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uint64 rt = extract_rt_9_8_7_6_5(instruction);
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uint64 rt = extract_rt_9_8_7_6_5(instruction);
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return rt != 0;
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return rt != 0;
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}
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}
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bool NMD::P16_BR1_cond(uint64 instruction)
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static bool P16_BR1_cond(uint64 instruction)
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{
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{
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uint64 u = extract_u_3_2_1_0__s1(instruction);
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uint64 u = extract_u_3_2_1_0__s1(instruction);
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return u != 0;
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return u != 0;
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}
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}
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bool NMD::PREF_S9__cond(uint64 instruction)
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static bool PREF_S9__cond(uint64 instruction)
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{
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{
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uint64 hint = extract_hint_25_24_23_22_21(instruction);
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uint64 hint = extract_hint_25_24_23_22_21(instruction);
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return hint != 31;
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return hint != 31;
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}
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}
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bool NMD::PREFE_cond(uint64 instruction)
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static bool PREFE_cond(uint64 instruction)
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{
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{
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uint64 hint = extract_hint_25_24_23_22_21(instruction);
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uint64 hint = extract_hint_25_24_23_22_21(instruction);
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return hint != 31;
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return hint != 31;
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}
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}
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bool NMD::SLTU_cond(uint64 instruction)
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static bool SLTU_cond(uint64 instruction)
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{
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{
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uint64 rd = extract_rd_15_14_13_12_11(instruction);
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uint64 rd = extract_rd_15_14_13_12_11(instruction);
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return rd != 0;
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return rd != 0;
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@ -16692,7 +16692,7 @@ NMD::Pool NMD::P_ADDIU[2] = {
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0xffe00000, 0x00000000, 0 , 0,
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0xffe00000, 0x00000000, 0 , 0,
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0x0 }, /* P.RI */
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0x0 }, /* P.RI */
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{ instruction , 0 , 0 , 32,
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{ instruction , 0 , 0 , 32,
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0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &NMD::ADDIU_32__cond ,
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0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &ADDIU_32__cond ,
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0x0 }, /* ADDIU[32] */
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0x0 }, /* ADDIU[32] */
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};
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};
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@ -16790,7 +16790,7 @@ NMD::Pool NMD::P_SLTU[2] = {
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0xfc00fbff, 0x20000390, 0 , 0,
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0xfc00fbff, 0x20000390, 0 , 0,
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0x0 }, /* P.DVP */
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0x0 }, /* P.DVP */
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{ instruction , 0 , 0 , 32,
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{ instruction , 0 , 0 , 32,
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0xfc0003ff, 0x20000390, &NMD::SLTU , &NMD::SLTU_cond ,
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0xfc0003ff, 0x20000390, &NMD::SLTU , &SLTU_cond ,
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0x0 }, /* SLTU */
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0x0 }, /* SLTU */
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};
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};
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@ -21335,7 +21335,7 @@ NMD::Pool NMD::P_PREF_S9_[2] = {
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0xffe07f00, 0xa7e01800, &NMD::SYNCI , 0,
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0xffe07f00, 0xa7e01800, &NMD::SYNCI , 0,
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0x0 }, /* SYNCI */
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0x0 }, /* SYNCI */
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{ instruction , 0 , 0 , 32,
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{ instruction , 0 , 0 , 32,
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0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &NMD::PREF_S9__cond ,
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0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &PREF_S9__cond ,
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0x0 }, /* PREF[S9] */
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0x0 }, /* PREF[S9] */
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};
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};
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@ -21547,7 +21547,7 @@ NMD::Pool NMD::P_PREFE[2] = {
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0xffe07f00, 0xa7e01a00, &NMD::SYNCIE , 0,
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0xffe07f00, 0xa7e01a00, &NMD::SYNCIE , 0,
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CP0_ | EVA_ }, /* SYNCIE */
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CP0_ | EVA_ }, /* SYNCIE */
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{ instruction , 0 , 0 , 32,
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{ instruction , 0 , 0 , 32,
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0xfc007f00, 0xa4001a00, &NMD::PREFE , &NMD::PREFE_cond ,
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0xfc007f00, 0xa4001a00, &NMD::PREFE , &PREFE_cond ,
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CP0_ | EVA_ }, /* PREFE */
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CP0_ | EVA_ }, /* PREFE */
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};
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};
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@ -21719,7 +21719,7 @@ NMD::Pool NMD::P_BALRSC[2] = {
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0xffe0f000, 0x48008000, &NMD::BRSC , 0,
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0xffe0f000, 0x48008000, &NMD::BRSC , 0,
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0x0 }, /* BRSC */
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0x0 }, /* BRSC */
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{ call_instruction , 0 , 0 , 32,
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{ call_instruction , 0 , 0 , 32,
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0xfc00f000, 0x48008000, &NMD::BALRSC , &NMD::BALRSC_cond ,
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0xfc00f000, 0x48008000, &NMD::BALRSC , &BALRSC_cond ,
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0x0 }, /* BALRSC */
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0x0 }, /* BALRSC */
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};
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};
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@ -22067,7 +22067,7 @@ NMD::Pool NMD::P16_MV[2] = {
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0xffe0 , 0x1000 , 0 , 0,
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0xffe0 , 0x1000 , 0 , 0,
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0x0 }, /* P16.RI */
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0x0 }, /* P16.RI */
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{ instruction , 0 , 0 , 16,
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{ instruction , 0 , 0 , 16,
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0xfc00 , 0x1000 , &NMD::MOVE , &NMD::MOVE_cond ,
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0xfc00 , 0x1000 , &NMD::MOVE , &MOVE_cond ,
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0x0 }, /* MOVE */
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0x0 }, /* MOVE */
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};
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};
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@ -22133,7 +22133,7 @@ NMD::Pool NMD::P_ADDIU_RS5_[2] = {
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0xffe8 , 0x9008 , &NMD::NOP_16_ , 0,
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0xffe8 , 0x9008 , &NMD::NOP_16_ , 0,
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0x0 }, /* NOP[16] */
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0x0 }, /* NOP[16] */
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{ instruction , 0 , 0 , 16,
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{ instruction , 0 , 0 , 16,
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0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &NMD::ADDIU_RS5__cond ,
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0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &ADDIU_RS5__cond ,
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0x0 }, /* ADDIU[RS5] */
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0x0 }, /* ADDIU[RS5] */
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};
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};
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@ -22170,10 +22170,10 @@ NMD::Pool NMD::P16_JRC[2] = {
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NMD::Pool NMD::P16_BR1[2] = {
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NMD::Pool NMD::P16_BR1[2] = {
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{ branch_instruction , 0 , 0 , 16,
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{ branch_instruction , 0 , 0 , 16,
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0xfc00 , 0xd800 , &NMD::BEQC_16_ , &NMD::BEQC_16__cond ,
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0xfc00 , 0xd800 , &NMD::BEQC_16_ , &BEQC_16__cond ,
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XMMS_ }, /* BEQC[16] */
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XMMS_ }, /* BEQC[16] */
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{ branch_instruction , 0 , 0 , 16,
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{ branch_instruction , 0 , 0 , 16,
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0xfc00 , 0xd800 , &NMD::BNEC_16_ , &NMD::BNEC_16__cond ,
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0xfc00 , 0xd800 , &NMD::BNEC_16_ , &BNEC_16__cond ,
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XMMS_ }, /* BNEC[16] */
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XMMS_ }, /* BNEC[16] */
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};
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};
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@ -22183,7 +22183,7 @@ NMD::Pool NMD::P16_BR[2] = {
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0xfc0f , 0xd800 , 0 , 0,
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0xfc0f , 0xd800 , 0 , 0,
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0x0 }, /* P16.JRC */
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0x0 }, /* P16.JRC */
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{ pool , P16_BR1 , 2 , 16,
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{ pool , P16_BR1 , 2 , 16,
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0xfc00 , 0xd800 , 0 , &NMD::P16_BR1_cond ,
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0xfc00 , 0xd800 , 0 , &P16_BR1_cond ,
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0x0 }, /* P16.BR1 */
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0x0 }, /* P16.BR1 */
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};
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};
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@ -64,6 +64,8 @@ typedef struct Dis_info {
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img_address m_pc;
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img_address m_pc;
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} Dis_info;
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} Dis_info;
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typedef bool (*conditional_function)(uint64 instruction);
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class NMD
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class NMD
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{
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{
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public:
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public:
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@ -75,7 +77,6 @@ private:
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typedef std::string(NMD:: *disassembly_function)(uint64 instruction,
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typedef std::string(NMD:: *disassembly_function)(uint64 instruction,
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Dis_info *info);
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Dis_info *info);
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typedef bool(NMD:: *conditional_function)(uint64 instruction);
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struct Pool {
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struct Pool {
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TABLE_ENTRY_TYPE type;
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TABLE_ENTRY_TYPE type;
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@ -94,17 +95,6 @@ private:
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TABLE_ENTRY_TYPE & type, const Pool *table, int table_size,
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TABLE_ENTRY_TYPE & type, const Pool *table, int table_size,
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Dis_info *info);
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Dis_info *info);
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bool ADDIU_32__cond(uint64 instruction);
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bool ADDIU_RS5__cond(uint64 instruction);
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bool BALRSC_cond(uint64 instruction);
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bool BEQC_16__cond(uint64 instruction);
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bool BNEC_16__cond(uint64 instruction);
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bool MOVE_cond(uint64 instruction);
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bool P16_BR1_cond(uint64 instruction);
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bool PREF_S9__cond(uint64 instruction);
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bool PREFE_cond(uint64 instruction);
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bool SLTU_cond(uint64 instruction);
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std::string ABS_D(uint64 instruction, Dis_info *info);
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std::string ABS_D(uint64 instruction, Dis_info *info);
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std::string ABS_S(uint64 instruction, Dis_info *info);
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std::string ABS_S(uint64 instruction, Dis_info *info);
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std::string ABSQ_S_PH(uint64 instruction, Dis_info *info);
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std::string ABSQ_S_PH(uint64 instruction, Dis_info *info);
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