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tricore insn bugfixes for qemu 8.0

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Merge tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu into staging

tricore insn bugfixes for qemu 8.0

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# gpg: Signature made Wed 08 Feb 2023 09:07:01 GMT
# gpg:                using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg:                issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu:
  tests/tcg/tricore: Add test for ld.h
  target/tricore: Fix OPC1_16_SRO_LD_H translation
  tests/tcg/tricore: Add LD.BU tests
  target/tricore: Fix OPC2_32_BO_LD_BU_PREINC
  tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests
  target/tricore: Fix OPC2_32_RRRR_DEXTR
  tests/tcg/tricore: Add tests for RRPW_DEXTR
  target/tricore: Fix RRPW_DEXTR
  tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
  target/tricore: Fix OPC2_32_RCRW_INSERT translation
  tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK
  target/tricore: Fix OPC2_32_RCRW_IMASK translation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-02-08 13:28:26 +00:00
commit 65417c2357
8 changed files with 223 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
target/tricore/translate.c
View File

@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
break;
case OPC1_16_SRO_LD_H:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
break;
case OPC1_16_SRO_LD_W:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
@ -4964,7 +4964,7 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_BU_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_LD_D_SHORTOFF:
CHECK_REG_PAIR(r1);
@ -5794,19 +5794,19 @@ static void decode_rcrw_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RCRW_IMASK:
tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_movi_tl(temp2, (1 << width) - 1);
tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
temp3 = tcg_temp_new();
tcg_gen_movi_tl(temp, width);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_temp_free(temp3);
break;
@ -8245,10 +8245,19 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
if (r1 == r2) {
tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
TCGv msw = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
tcg_gen_subfi_tl(msw, 32, tmp_pos);
tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
/*
* if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
* behaviour. So check that case here and set the low bits to zero
* which effectivly returns cpu_gpr_d[r1]
*/
tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
tcg_temp_free(msw);
}
break;
case OPC2_32_RRRR_EXTR:
@ -8706,15 +8715,9 @@ static void decode_32Bit_opc(DisasContext *ctx)
r2 = MASK_OP_RRPW_S2(ctx->opcode);
r3 = MASK_OP_RRPW_D(ctx->opcode);
const16 = MASK_OP_RRPW_POS(ctx->opcode);
if (r1 == r2) {
tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
} else {
temp = tcg_temp_new();
tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
tcg_temp_free(temp);
}
tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
32 - const16);
break;
/* RRR Format */
case OPCM_32_RRR_COND_SELECT:

5
tests/tcg/tricore/Makefile.softmmu-target
View File

@ -6,10 +6,15 @@ ASFLAGS =
TESTS += test_abs.tst
TESTS += test_bmerge.tst
TESTS += test_clz.tst
TESTS += test_dextr.tst
TESTS += test_dvstep.tst
TESTS += test_fadd.tst
TESTS += test_fmul.tst
TESTS += test_ftoi.tst
TESTS += test_imask.tst
TESTS += test_insert.tst
TESTS += test_ld_bu.tst
TESTS += test_ld_h.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst

76
tests/tcg/tricore/macros.h
View File

@ -4,19 +4,28 @@
movh DREG_TEMP_LI, up:val; \
or reg, reg, DREG_TEMP_LI; \
#define LIA(reg, val) \
LI(DREG_TEMP, val) \
mov.a reg, DREG_TEMP;
/* Address definitions */
#define TESTDEV_ADDR 0xf0000000
/* Register definitions */
#define DREG_RS1 %d0
#define DREG_RS2 %d1
#define DREG_RS3 %d4
#define DREG_CALC_RESULT %d1
#define DREG_CALC_PSW %d2
#define DREG_CORRECT_PSW %d3
#define DREG_RS3 %d2
#define DREG_CALC_RESULT %d3
#define DREG_CALC_PSW %d4
#define DREG_CORRECT_PSW %d5
#define DREG_TEMP_LI %d10
#define DREG_TEMP %d11
#define DREG_TEST_NUM %d14
#define DREG_CORRECT_RESULT %d15
#define DREG_CORRECT_RESULT_2 %d13
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
#define MEM_BASE_ADDR 0xd0000000
#define DREG_DEV_ADDR %a15
@ -60,11 +69,36 @@ test_ ## num: \
mov DREG_TEST_NUM, num; \
jne DREG_CALC_PSW, DREG_CORRECT_PSW, fail;
#define TEST_LD(insn, num, result, addr_result, ld_pattern) \
test_ ## num: \
LIA(AREG_ADDR, test_data) \
insn DREG_CALC_RESULT, ld_pattern; \
LI(DREG_CORRECT_RESULT, result) \
mov DREG_TEST_NUM, num; \
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail; \
mov.d DREG_CALC_RESULT, AREG_ADDR; \
LI(DREG_CORRECT_RESULT, addr_result) \
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
#define TEST_LD_SRO(insn, num, result, addr_result, ld_pattern) \
test_ ## num: \
LIA(AREG_ADDR, test_data) \
insn %d15, ld_pattern; \
LI(DREG_CORRECT_RESULT_2, result) \
mov DREG_TEST_NUM, num; \
jne %d15, DREG_CORRECT_RESULT_2, fail; \
mov.d DREG_CALC_RESULT, AREG_ADDR; \
LI(DREG_CORRECT_RESULT, addr_result) \
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
/* Actual test case type
* e.g inst %dX, %dY -> TEST_D_D
* inst %dX, %dY, %dZ -> TEST_D_DD
* inst %eX, %dY, %dZ -> TEST_E_DD
*/
#define TEST_D_D(insn, num, result, rs1) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@ -78,6 +112,15 @@ test_ ## num: \
insn DREG_CORRECT_RESULT, DREG_RS1; \
)
#define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
LI(DREG_RS2, rs2); \
LI(DREG_RS3, rs3); \
rstv; \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
)
#define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
@ -95,6 +138,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
)
#define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
LI(DREG_RS2, rs2); \
rstv; \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
#define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
@ -103,6 +154,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
LI(DREG_RS2, rs1); \
rstv; \
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
)
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
@ -111,6 +170,15 @@ test_ ## num: \
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
)
#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(DREG_RS1, rs1); \
rstv; \
insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2); \
)
/* Pass/Fail handling part */
#define TEST_PASSFAIL \
j pass; \

75
tests/tcg/tricore/test_dextr.S Normal file
View File

@ -0,0 +1,75 @@
#include "macros.h"
.text
.global _start
_start:
# insn num result rs1 rs2 imm
# | | | | | |
TEST_D_DDI(dextr, 1, 0xabcdef01, 0xabcdef01, 0x23456789, 0)
TEST_D_DDI(dextr, 2, 0x579bde02, 0xabcdef01, 0x23456789, 1)
TEST_D_DDI(dextr, 3, 0xaf37bc04, 0xabcdef01, 0x23456789, 2)
TEST_D_DDI(dextr, 4, 0x5e6f7809, 0xabcdef01, 0x23456789, 3)
TEST_D_DDI(dextr, 5, 0xbcdef012, 0xabcdef01, 0x23456789, 4)
TEST_D_DDI(dextr, 6, 0x79bde024, 0xabcdef01, 0x23456789, 5)
TEST_D_DDI(dextr, 7, 0xf37bc048, 0xabcdef01, 0x23456789, 6)
TEST_D_DDI(dextr, 8, 0xe6f78091, 0xabcdef01, 0x23456789, 7)
TEST_D_DDI(dextr, 9, 0xcdef0123, 0xabcdef01, 0x23456789, 8)
TEST_D_DDI(dextr, 10, 0x9bde0246, 0xabcdef01, 0x23456789, 9)
TEST_D_DDI(dextr, 11, 0x37bc048d, 0xabcdef01, 0x23456789, 10)
TEST_D_DDI(dextr, 12, 0x6f78091a, 0xabcdef01, 0x23456789, 11)
TEST_D_DDI(dextr, 13, 0xdef01234, 0xabcdef01, 0x23456789, 12)
TEST_D_DDI(dextr, 14, 0xbde02468, 0xabcdef01, 0x23456789, 13)
TEST_D_DDI(dextr, 15, 0x7bc048d1, 0xabcdef01, 0x23456789, 14)
TEST_D_DDI(dextr, 16, 0xf78091a2, 0xabcdef01, 0x23456789, 15)
TEST_D_DDI(dextr, 17, 0xef012345, 0xabcdef01, 0x23456789, 16)
TEST_D_DDI(dextr, 18, 0xde02468a, 0xabcdef01, 0x23456789, 17)
TEST_D_DDI(dextr, 19, 0xbc048d15, 0xabcdef01, 0x23456789, 18)
TEST_D_DDI(dextr, 20, 0x78091a2b, 0xabcdef01, 0x23456789, 19)
TEST_D_DDI(dextr, 21, 0xf0123456, 0xabcdef01, 0x23456789, 20)
TEST_D_DDI(dextr, 22, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
TEST_D_DDI(dextr, 23, 0xc048d159, 0xabcdef01, 0x23456789, 22)
TEST_D_DDI(dextr, 24, 0x8091a2b3, 0xabcdef01, 0x23456789, 23)
TEST_D_DDI(dextr, 25, 0x01234567, 0xabcdef01, 0x23456789, 24)
TEST_D_DDI(dextr, 26, 0x02468acf, 0xabcdef01, 0x23456789, 25)
TEST_D_DDI(dextr, 27, 0x048d159e, 0xabcdef01, 0x23456789, 26)
TEST_D_DDI(dextr, 28, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
TEST_D_DDI(dextr, 29, 0x12345678, 0xabcdef01, 0x23456789, 28)
TEST_D_DDI(dextr, 30, 0x2468acf1, 0xabcdef01, 0x23456789, 29)
TEST_D_DDI(dextr, 31, 0x48d159e2, 0xabcdef01, 0x23456789, 30)
TEST_D_DDI(dextr, 32, 0x91a2b3c4, 0xabcdef01, 0x23456789, 31)
# insn num result rs1 rs2 rs3
# | | | | | |
TEST_D_DDD(dextr, 33, 0xabcdef01, 0xabcdef01, 0x23456789, 0)
TEST_D_DDD(dextr, 34, 0x579bde02, 0xabcdef01, 0x23456789, 1)
TEST_D_DDD(dextr, 35, 0xaf37bc04, 0xabcdef01, 0x23456789, 2)
TEST_D_DDD(dextr, 36, 0x5e6f7809, 0xabcdef01, 0x23456789, 3)
TEST_D_DDD(dextr, 37, 0xbcdef012, 0xabcdef01, 0x23456789, 4)
TEST_D_DDD(dextr, 38, 0x79bde024, 0xabcdef01, 0x23456789, 5)
TEST_D_DDD(dextr, 39, 0xf37bc048, 0xabcdef01, 0x23456789, 6)
TEST_D_DDD(dextr, 40, 0xe6f78091, 0xabcdef01, 0x23456789, 7)
TEST_D_DDD(dextr, 41, 0xcdef0123, 0xabcdef01, 0x23456789, 8)
TEST_D_DDD(dextr, 42, 0x9bde0246, 0xabcdef01, 0x23456789, 9)
TEST_D_DDD(dextr, 43, 0x37bc048d, 0xabcdef01, 0x23456789, 10)
TEST_D_DDD(dextr, 44, 0x6f78091a, 0xabcdef01, 0x23456789, 11)
TEST_D_DDD(dextr, 45, 0xdef01234, 0xabcdef01, 0x23456789, 12)
TEST_D_DDD(dextr, 46, 0xbde02468, 0xabcdef01, 0x23456789, 13)
TEST_D_DDD(dextr, 47, 0x7bc048d1, 0xabcdef01, 0x23456789, 14)
TEST_D_DDD(dextr, 48, 0xf78091a2, 0xabcdef01, 0x23456789, 15)
TEST_D_DDD(dextr, 49, 0xef012345, 0xabcdef01, 0x23456789, 16)
TEST_D_DDD(dextr, 51, 0xde02468a, 0xabcdef01, 0x23456789, 17)
TEST_D_DDD(dextr, 52, 0xbc048d15, 0xabcdef01, 0x23456789, 18)
TEST_D_DDD(dextr, 53, 0x78091a2b, 0xabcdef01, 0x23456789, 19)
TEST_D_DDD(dextr, 54, 0xf0123456, 0xabcdef01, 0x23456789, 20)
TEST_D_DDD(dextr, 55, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
TEST_D_DDD(dextr, 56, 0xc048d159, 0xabcdef01, 0x23456789, 22)
TEST_D_DDD(dextr, 57, 0x8091a2b3, 0xabcdef01, 0x23456789, 23)
TEST_D_DDD(dextr, 58, 0x01234567, 0xabcdef01, 0x23456789, 24)
TEST_D_DDD(dextr, 59, 0x02468acf, 0xabcdef01, 0x23456789, 25)
TEST_D_DDD(dextr, 60, 0x048d159e, 0xabcdef01, 0x23456789, 26)
TEST_D_DDD(dextr, 61, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
TEST_D_DDD(dextr, 62, 0x12345678, 0xabcdef01, 0x23456789, 28)
TEST_D_DDD(dextr, 63, 0x2468acf1, 0xabcdef01, 0x23456789, 29)
TEST_D_DDD(dextr, 64, 0x48d159e2, 0xabcdef01, 0x23456789, 30)
TEST_D_DDD(dextr, 65, 0x91a2b3c4, 0xabcdef01, 0x23456789, 31)
TEST_PASSFAIL

10
tests/tcg/tricore/test_imask.S Normal file
View File

@ -0,0 +1,10 @@
#include "macros.h"
.text
.global _start
_start:
# res[31:0]
# insn num res[63:32] | imm1 rs1 imm2
# | | | | | | |
TEST_E_IDI(imask, 1, 0x000f0000, 0x00050000, 0x5, 0x10, 0x4)
TEST_PASSFAIL

9
tests/tcg/tricore/test_insert.S Normal file
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@ -0,0 +1,9 @@
#include "macros.h"
.text
.global _start
_start:
# insn num result rs1 imm1 rs2 imm2
# | | | | | | |
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
TEST_PASSFAIL

15
tests/tcg/tricore/test_ld_bu.S Normal file
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#include "macros.h"
.data
test_data:
.word 0xaffedead
.word 0x001122ff
.text
.global _start
_start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
TEST_PASSFAIL

15
tests/tcg/tricore/test_ld_h.S Normal file
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#include "macros.h"
.data
test_data:
.word 0xaffedead
.word 0x001122ff
.text
.global _start
_start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
TEST_LD (ld.h, 1, 0xffffaffe, MEM_BASE_ADDR, [AREG_ADDR]2)
TEST_LD_SRO(ld.h, 2, 0x000022ff, MEM_BASE_ADDR, [AREG_ADDR]4)
TEST_PASSFAIL