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target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR

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UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR
index E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.

This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.

Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191011074103.30393-3-tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Tao Xu 2019-10-11 15:41:03 +08:00 committed by Paolo Bonzini
parent 67192a298f
commit 6508799707
3 changed files with 35 additions and 0 deletions
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2
target/i386/cpu.h
View File

@ -452,6 +452,7 @@ typedef enum X86Seg {
#define MSR_IA32_BNDCFGS 0x00000d90
#define MSR_IA32_XSS 0x00000da0
#define MSR_IA32_UMWAIT_CONTROL 0xe1
#define MSR_IA32_VMX_BASIC 0x00000480
#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
@ -1587,6 +1588,7 @@ typedef struct CPUX86State {
uint16_t fpregs_format_vmstate;
uint64_t xss;
uint32_t umwait;
TPRAccess tpr_access_type;

13
target/i386/kvm.c
View File

@ -95,6 +95,7 @@ static bool has_msr_hv_stimer;
static bool has_msr_hv_frequencies;
static bool has_msr_hv_reenlightenment;
static bool has_msr_xss;
static bool has_msr_umwait;
static bool has_msr_spec_ctrl;
static bool has_msr_virt_ssbd;
static bool has_msr_smi_count;
@ -2005,6 +2006,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_XSS:
has_msr_xss = true;
break;
case MSR_IA32_UMWAIT_CONTROL:
has_msr_umwait = true;
break;
case HV_X64_MSR_CRASH_CTL:
has_msr_hv_crash = true;
break;
@ -2684,6 +2688,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_xss) {
kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
}
if (has_msr_umwait) {
kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
}
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
@ -3097,6 +3104,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_xss) {
kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
}
if (has_msr_umwait) {
kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
}
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
@ -3349,6 +3359,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_XSS:
env->xss = msrs[i].data;
break;
case MSR_IA32_UMWAIT_CONTROL:
env->umwait = msrs[i].data;
break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {

20
target/i386/machine.c
View File

@ -943,6 +943,25 @@ static const VMStateDescription vmstate_xss = {
}
};
static bool umwait_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return env->umwait != 0;
}
static const VMStateDescription vmstate_umwait = {
.name = "cpu/umwait",
.version_id = 1,
.minimum_version_id = 1,
.needed = umwait_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.umwait, X86CPU),
VMSTATE_END_OF_LIST()
}
};
#ifdef TARGET_X86_64
static bool pkru_needed(void *opaque)
{
@ -1391,6 +1410,7 @@ VMStateDescription vmstate_x86_cpu = {
&vmstate_msr_hyperv_reenlightenment,
&vmstate_avx512,
&vmstate_xss,
&vmstate_umwait,
&vmstate_tsc_khz,
&vmstate_msr_smi_count,
#ifdef TARGET_X86_64