hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object
This object represents the PLLs and their channels. The PLLs allow for a more fine-grained control of the clocks frequency. The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Arnaud Minier
Peter Maydell
parent
ec7d83acbd
commit
6487653efd
@ -164,6 +164,157 @@ static void clock_mux_set_source(RccClockMuxState *mux, RccClockMuxSource src)
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clock_mux_update(mux);
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}
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static void pll_update(RccPllState *pll)
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{
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uint64_t vco_freq, old_channel_freq, channel_freq;
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int i;
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/* The common PLLM factor is handled by the PLL mux */
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vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1);
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for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
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if (!pll->channel_exists[i]) {
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continue;
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}
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old_channel_freq = clock_get_hz(pll->channels[i]);
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if (!pll->enabled ||
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!pll->channel_enabled[i] ||
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!pll->channel_divider[i]) {
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channel_freq = 0;
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} else {
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channel_freq = muldiv64(vco_freq,
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1,
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pll->channel_divider[i]);
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}
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/* No change, early continue to avoid log spam and useless propagation */
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if (old_channel_freq == channel_freq) {
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continue;
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}
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clock_update_hz(pll->channels[i], channel_freq);
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trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq,
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old_channel_freq, channel_freq);
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}
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}
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static void pll_src_update(void *opaque, ClockEvent event)
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{
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RccPllState *s = opaque;
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pll_update(s);
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}
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static void pll_init(Object *obj)
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{
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RccPllState *s = RCC_PLL(obj);
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size_t i;
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s->in = qdev_init_clock_in(DEVICE(s), "in",
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pll_src_update, s, ClockUpdate);
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const char *names[] = {
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"out-p", "out-q", "out-r",
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};
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for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
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s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]);
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}
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}
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static void pll_reset_hold(Object *obj)
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{ }
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static const VMStateDescription pll_vmstate = {
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.name = TYPE_RCC_PLL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(id, RccPllState),
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VMSTATE_CLOCK(in, RccPllState),
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VMSTATE_ARRAY_CLOCK(channels, RccPllState,
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RCC_NUM_CHANNEL_PLL_OUT),
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VMSTATE_BOOL(enabled, RccPllState),
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VMSTATE_UINT32(vco_multiplier, RccPllState),
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VMSTATE_BOOL_ARRAY(channel_enabled, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
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VMSTATE_BOOL_ARRAY(channel_exists, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
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VMSTATE_UINT32_ARRAY(channel_divider, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pll_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = pll_reset_hold;
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dc->vmsd = &pll_vmstate;
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}
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static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)
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{
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if (pll->vco_multiplier == vco_multiplier) {
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return;
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}
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if (vco_multiplier < 8 || vco_multiplier > 86) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: VCO multiplier is out of bound (%u) for PLL %u\n",
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__func__, vco_multiplier, pll->id);
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return;
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}
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trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id,
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pll->vco_multiplier, vco_multiplier);
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pll->vco_multiplier = vco_multiplier;
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pll_update(pll);
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}
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static void pll_set_enable(RccPllState *pll, bool enabled)
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{
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if (pll->enabled == enabled) {
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return;
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}
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pll->enabled = enabled;
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pll_update(pll);
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}
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static void pll_set_channel_enable(RccPllState *pll,
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PllCommonChannels channel,
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bool enabled)
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{
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if (pll->channel_enabled[channel] == enabled) {
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return;
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}
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if (enabled) {
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trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel);
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} else {
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trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel);
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}
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pll->channel_enabled[channel] = enabled;
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pll_update(pll);
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}
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static void pll_set_channel_divider(RccPllState *pll,
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PllCommonChannels channel,
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uint32_t divider)
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{
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if (pll->channel_divider[channel] == divider) {
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return;
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}
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trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id,
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channel, pll->channel_divider[channel], divider);
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pll->channel_divider[channel] = divider;
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pll_update(pll);
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}
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static void rcc_update_irq(Stm32l4x5RccState *s)
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{
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if (s->cifr & CIFR_IRQ_MASK) {
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@ -473,6 +624,11 @@ static void stm32l4x5_rcc_init(Object *obj)
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qdev_init_clocks(DEVICE(s), stm32l4x5_rcc_clocks);
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for (i = 0; i < RCC_NUM_PLL; i++) {
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object_initialize_child(obj, "pll[*]",
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&s->plls[i], TYPE_RCC_PLL);
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}
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for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
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object_initialize_child(obj, "clock[*]",
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@ -543,6 +699,16 @@ static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp)
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return;
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}
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for (i = 0; i < RCC_NUM_PLL; i++) {
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RccPllState *pll = &s->plls[i];
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clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out);
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if (!qdev_realize(DEVICE(pll), NULL, errp)) {
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return;
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}
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}
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for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
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RccClockMuxState *clock_mux = &s->clock_muxes[i];
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@ -563,6 +729,10 @@ static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp)
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clock_mux_set_source(&s->clock_muxes[0], RCC_CLOCK_MUX_SRC_GND);
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clock_mux_set_enable(&s->clock_muxes[0], true);
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clock_mux_set_factor(&s->clock_muxes[0], 1, 1);
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pll_set_channel_divider(&s->plls[0], 0, 1);
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pll_set_enable(&s->plls[0], true);
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pll_set_channel_enable(&s->plls[0], 0, true);
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pll_set_vco_multiplier(&s->plls[0], 1);
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}
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static Property stm32l4x5_rcc_properties[] = {
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@ -600,6 +770,12 @@ static const TypeInfo stm32l4x5_rcc_types[] = {
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.instance_size = sizeof(RccClockMuxState),
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.instance_init = clock_mux_init,
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.class_init = clock_mux_class_init,
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}, {
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.name = TYPE_RCC_PLL,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(RccPllState),
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.instance_init = pll_init,
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.class_init = pll_class_init,
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}
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};
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@ -182,6 +182,11 @@ stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled"
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stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)"
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stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source changed: from %u to %u"
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stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32
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stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier changed (%u -> %u)"
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stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u enabled"
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stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u disabled"
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stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: divider changed (%u -> %u)"
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stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64
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# tz-mpc.c
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tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
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@ -26,6 +26,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC)
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/* In the Stm32l4x5 clock tree, mux have at most 7 sources */
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#define RCC_NUM_CLOCK_MUX_SRC 7
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typedef enum PllCommonChannels {
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RCC_PLL_COMMON_CHANNEL_P = 0,
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RCC_PLL_COMMON_CHANNEL_Q = 1,
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RCC_PLL_COMMON_CHANNEL_R = 2,
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RCC_NUM_CHANNEL_PLL_OUT = 3
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} PllCommonChannels;
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/* NB: Prescaler are assimilated to mux with one source and one output */
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typedef enum RccClockMux {
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/* Internal muxes that arent't exposed publicly to other peripherals */
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@ -124,6 +133,14 @@ typedef enum RccClockMux {
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RCC_NUM_CLOCK_MUX
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} RccClockMux;
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typedef enum RccPll {
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RCC_PLL_PLL,
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RCC_PLL_PLLSAI1,
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RCC_PLL_PLLSAI2,
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RCC_NUM_PLL
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} RccPll;
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typedef struct RccClockMuxState {
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DeviceState parent_obj;
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@ -142,6 +159,26 @@ typedef struct RccClockMuxState {
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struct RccClockMuxState *backref[RCC_NUM_CLOCK_MUX_SRC];
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} RccClockMuxState;
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typedef struct RccPllState {
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DeviceState parent_obj;
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RccPll id;
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Clock *in;
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uint32_t vco_multiplier;
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Clock *channels[RCC_NUM_CHANNEL_PLL_OUT];
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/* Global pll enabled flag */
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bool enabled;
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/* 'enabled' refers to the runtime configuration */
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bool channel_enabled[RCC_NUM_CHANNEL_PLL_OUT];
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/*
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* 'exists' refers to the physical configuration
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* It should only be set at pll initialization.
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* e.g. pllsai2 doesn't have a Q output.
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*/
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bool channel_exists[RCC_NUM_CHANNEL_PLL_OUT];
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uint32_t channel_divider[RCC_NUM_CHANNEL_PLL_OUT];
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} RccPllState;
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struct Stm32l4x5RccState {
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SysBusDevice parent_obj;
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@ -187,6 +224,9 @@ struct Stm32l4x5RccState {
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Clock *sai1_extclk;
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Clock *sai2_extclk;
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/* PLLs */
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RccPllState plls[RCC_NUM_PLL];
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/* Muxes ~= outputs */
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RccClockMuxState clock_muxes[RCC_NUM_CLOCK_MUX];
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@ -22,7 +22,10 @@
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#include "hw/misc/stm32l4x5_rcc.h"
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#define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
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#define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
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OBJECT_DECLARE_SIMPLE_TYPE(RccClockMuxState, RCC_CLOCK_MUX)
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OBJECT_DECLARE_SIMPLE_TYPE(RccPllState, RCC_PLL)
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/* Register map */
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REG32(CR, 0x00)
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@ -285,6 +288,25 @@ REG32(CSR, 0x94)
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R_CSR_FWRSTF_MASK | \
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R_CSR_LSIRDY_MASK)
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/* Pll Channels */
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enum PllChannels {
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RCC_PLL_CHANNEL_PLLSAI3CLK = 0,
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RCC_PLL_CHANNEL_PLL48M1CLK = 1,
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RCC_PLL_CHANNEL_PLLCLK = 2,
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};
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enum PllSai1Channels {
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RCC_PLLSAI1_CHANNEL_PLLSAI1CLK = 0,
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RCC_PLLSAI1_CHANNEL_PLL48M2CLK = 1,
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RCC_PLLSAI1_CHANNEL_PLLADC1CLK = 2,
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};
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enum PllSai2Channels {
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RCC_PLLSAI2_CHANNEL_PLLSAI2CLK = 0,
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/* No Q channel */
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RCC_PLLSAI2_CHANNEL_PLLADC2CLK = 2,
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};
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typedef enum RccClockMuxSource {
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RCC_CLOCK_MUX_SRC_GND = 0,
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RCC_CLOCK_MUX_SRC_HSI,
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