omap_gpmc/nseries/tusb6010: convert to memory API
Somewhat clumsy since it needs a variable sized region. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
d09871f69c
commit
64066a8fb6
@ -17,6 +17,7 @@
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef hw_omap_h
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#include "memory.h"
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# define hw_omap_h "omap.h"
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# define OMAP_EMIFS_BASE 0x00000000
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@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
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struct omap_gpmc_s;
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struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
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void omap_gpmc_reset(struct omap_gpmc_s *s);
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
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void (*base_upd)(void *opaque, target_phys_addr_t new),
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void (*unmap)(void *opaque), void *opaque);
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@ -21,10 +21,13 @@
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#include "hw.h"
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#include "flash.h"
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#include "omap.h"
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#include "memory.h"
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#include "exec-memory.h"
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/* General-Purpose Memory Controller */
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struct omap_gpmc_s {
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t sysconfig;
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uint16_t irqst;
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@ -39,7 +42,8 @@ struct omap_gpmc_s {
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uint32_t config[7];
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target_phys_addr_t base;
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size_t size;
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int iomemtype;
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MemoryRegion *iomem;
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MemoryRegion container;
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void (*base_update)(void *opaque, target_phys_addr_t new);
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void (*unmap)(void *opaque);
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void *opaque;
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@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
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* constant), the mask should cause wrapping of the address space, so
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* that the same memory becomes accessible at every <i>size</i> bytes
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* starting from <i>base</i>. */
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if (f->iomemtype)
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cpu_register_physical_memory(f->base, f->size, f->iomemtype);
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if (f->iomem) {
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memory_region_init(&f->container, "omap-gpmc-file", f->size);
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memory_region_add_subregion(&f->container, 0, f->iomem);
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memory_region_add_subregion(get_system_memory(), f->base,
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&f->container);
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}
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if (f->base_update)
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f->base_update(f->opaque, f->base);
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@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
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if (f->size) {
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if (f->unmap)
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f->unmap(f->opaque);
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if (f->iomemtype)
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cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
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if (f->iomem) {
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memory_region_del_subregion(get_system_memory(), &f->container);
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memory_region_del_subregion(&f->container, f->iomem);
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memory_region_destroy(&f->container);
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}
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f->base = 0;
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f->size = 0;
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}
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@ -132,12 +143,17 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
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ecc_reset(&s->ecc[i]);
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}
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static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
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static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4) {
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return omap_badwidth_read32(opaque, addr);
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}
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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return 0x20;
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@ -230,12 +246,16 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
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}
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static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4) {
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return omap_badwidth_write32(opaque, addr, value);
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}
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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case 0x014: /* GPMC_SYSSTATUS */
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@ -249,7 +269,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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case 0x010: /* GPMC_SYSCONFIG */
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if ((value >> 3) == 0x3)
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fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
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fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
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__FUNCTION__, value >> 3);
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if (value & 2)
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omap_gpmc_reset(s);
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@ -369,34 +389,26 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
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omap_badwidth_read32, /* TODO */
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omap_badwidth_read32, /* TODO */
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omap_gpmc_read,
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};
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static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
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omap_badwidth_write32, /* TODO */
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omap_badwidth_write32, /* TODO */
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omap_gpmc_write,
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static const MemoryRegionOps omap_gpmc_ops = {
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.read = omap_gpmc_read,
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.write = omap_gpmc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
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{
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int iomemtype;
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struct omap_gpmc_s *s = (struct omap_gpmc_s *)
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g_malloc0(sizeof(struct omap_gpmc_s));
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omap_gpmc_reset(s);
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iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
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omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x1000, iomemtype);
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memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
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memory_region_add_subregion(get_system_memory(), base, &s->iomem);
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return s;
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}
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
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void (*base_upd)(void *opaque, target_phys_addr_t new),
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void (*unmap)(void *opaque), void *opaque)
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{
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@ -408,7 +420,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
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}
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f = &s->cs_file[cs];
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f->iomemtype = iomemtype;
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f->iomem = iomem;
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f->base_update = base_upd;
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f->unmap = unmap;
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f->opaque = opaque;
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@ -26,7 +26,7 @@
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#include "tusb6010.h"
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struct TUSBState {
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int iomemtype[2];
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MemoryRegion iomem[2];
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qemu_irq irq;
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MUSBState *musb;
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QEMUTimer *otg_timer;
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@ -234,14 +234,14 @@ struct TUSBState {
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#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
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#define TUSB_PROD_TEST_RESET_VAL 0xa596
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int tusb6010_sync_io(TUSBState *s)
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MemoryRegion *tusb6010_sync_io(TUSBState *s)
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{
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return s->iomemtype[0];
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return &s->iomem[0];
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}
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int tusb6010_async_io(TUSBState *s)
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MemoryRegion *tusb6010_async_io(TUSBState *s)
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{
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return s->iomemtype[1];
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return &s->iomem[1];
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}
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static void tusb_intr_update(TUSBState *s)
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@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
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}
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}
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static CPUReadMemoryFunc * const tusb_async_readfn[] = {
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tusb_async_readb,
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tusb_async_readh,
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tusb_async_readw,
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};
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static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
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tusb_async_writeb,
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tusb_async_writeh,
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tusb_async_writew,
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static const MemoryRegionOps tusb_async_ops = {
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.old_mmio = {
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.read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
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.write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void tusb_otg_tick(void *opaque)
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@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
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s->mask = 0xffffffff;
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s->intr = 0x00000000;
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s->otg_timer_val = 0;
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s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
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tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
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memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
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UINT32_MAX);
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s->irq = intr;
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s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
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s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
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@ -16,10 +16,13 @@
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#ifndef TUSB6010_H
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#define TUSB6010_H
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#include "targphys.h"
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#include "memory.h"
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typedef struct TUSBState TUSBState;
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TUSBState *tusb6010_init(qemu_irq intr);
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int tusb6010_sync_io(TUSBState *s);
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int tusb6010_async_io(TUSBState *s);
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MemoryRegion *tusb6010_sync_io(TUSBState *s);
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MemoryRegion *tusb6010_async_io(TUSBState *s);
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void tusb6010_power(TUSBState *s, int on);
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#endif
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