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gt64xxx: fix decoding of ISD register

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The GT64xxx's internal registers can be placed above the first 4 GiB
in the address space, but not above the first 64 GiB.  Correctly cast
the register to a 64-bit integer, and mask away bits above bit 35.

Datasheet at http://pdf.datasheetarchive.com/datasheetsmain/Datasheets-33/DSA-655889.pdf
(bug reported by Coverity).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Paolo Bonzini 2015-11-06 16:34:06 +01:00 committed by Michael Tokarev
parent fccd35a046
commit 63fc7375d6
1 changed files with 2 additions and 1 deletions
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3
hw/mips/gt64xxx_pci.c
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@ -275,7 +275,8 @@ static void check_reserved_space (hwaddr *start,
static void gt64120_isd_mapping(GT64120State *s) static void gt64120_isd_mapping(GT64120State *s)
{ {
hwaddr start = s->regs[GT_ISD] << 21; /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
hwaddr length = 0x1000; hwaddr length = 0x1000;
if (s->ISD_length) { if (s->ISD_length) {