From 6c8cec822f153bb5e2871bdb309d90bcb750c24c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 24 Sep 2024 23:58:00 +0200 Subject: [PATCH 01/29] target/microblaze: Alias CPU endianness property as 'little-endian' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Alias the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-2-philmd@linaro.org> Reviewed-by: Edgar E. Iglesias Message-Id: <3f61b85c-9382-4520-a1ce-5476eb16fb56@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- target/microblaze/cpu.c | 10 ++++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index b4183c5267..df808ac323 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -90,7 +90,7 @@ petalogix_ml605_init(MachineState *machine) object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, &error_abort); - object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort); + object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index 1bfc9641d2..43608c2dca 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -90,7 +90,7 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true, &error_abort); object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "endianness", true, + object_property_set_bool(OBJECT(&s->cpu), "little-endian", true, &error_abort); object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b", &error_abort); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 135947ee80..b322f06077 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -328,9 +328,16 @@ static void mb_cpu_initfn(Object *obj) qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif + + /* Restricted 'endianness' property is equivalent of 'little-endian' */ + object_property_add_alias(obj, "little-endian", obj, "endianness"); } static Property mb_properties[] = { + /* + * Following properties are used by Xilinx DTS conversion tool + * do not rename them. + */ DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, false), @@ -387,6 +394,9 @@ static Property mb_properties[] = { DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), + /* + * End of properties reserved by Xilinx DTS conversion tool. + */ DEFINE_PROP_END_OF_LIST(), }; From 181b3a7bb03a9448d4f1a9c46fef1c1090586fe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 25 Sep 2024 00:08:12 +0200 Subject: [PATCH 02/29] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The petalogix-ml605 machine was explicitly added as little-endian only machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU little-endian ref design"). Mark the big-endian version as deprecated. When the xlnx-zynqmp-pmu machine's CPU was added in commit 133d23b3ad1 ("xlnx-zynqmp-pmu: Add the CPU and memory"), its 'endianness' property was set to %true, thus wired in little endianness. Both machine are included in the big-endian system binary, while their CPU is working in little-endian. Unlikely to work as it. Deprecate now as broken config so we can remove soon. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.22564-3-philmd@linaro.org> --- configs/devices/microblaze-softmmu/default.mak | 2 -- configs/devices/microblazeel-softmmu/default.mak | 5 ++++- docs/about/deprecated.rst | 6 ++++++ hw/microblaze/petalogix_ml605_mmu.c | 7 ++++++- hw/microblaze/xlnx-zynqmp-pmu.c | 8 ++++++-- 5 files changed, 22 insertions(+), 6 deletions(-) diff --git a/configs/devices/microblaze-softmmu/default.mak b/configs/devices/microblaze-softmmu/default.mak index 583e3959bb..7894106465 100644 --- a/configs/devices/microblaze-softmmu/default.mak +++ b/configs/devices/microblaze-softmmu/default.mak @@ -2,5 +2,3 @@ # Boards are selected by default, uncomment to keep out of the build. # CONFIG_PETALOGIX_S3ADSP1800=n -# CONFIG_PETALOGIX_ML605=n -# CONFIG_XLNX_ZYNQMP_PMU=n diff --git a/configs/devices/microblazeel-softmmu/default.mak b/configs/devices/microblazeel-softmmu/default.mak index 29f7f13816..4c1086435b 100644 --- a/configs/devices/microblazeel-softmmu/default.mak +++ b/configs/devices/microblazeel-softmmu/default.mak @@ -1,3 +1,6 @@ # Default configuration for microblazeel-softmmu -include ../microblaze-softmmu/default.mak +# Boards are selected by default, uncomment to keep out of the build. +# CONFIG_PETALOGIX_S3ADSP1800=n +# CONFIG_PETALOGIX_ML605=n +# CONFIG_XLNX_ZYNQMP_PMU=n diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 720d4eec8a..d8dc29d0a4 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -271,6 +271,12 @@ BMC and a witherspoon like OpenPOWER system. It was used for bring up of the AST2600 SoC in labs. It can be easily replaced by the ``rainier-bmc`` machine which is a real product. +Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian +CPUs. Big endian support is not tested. + Backend options --------------- diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index df808ac323..61e47d8398 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -213,7 +213,12 @@ petalogix_ml605_init(MachineState *machine) static void petalogix_ml605_machine_init(MachineClass *mc) { - mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian"; +#if TARGET_BIG_ENDIAN + mc->desc = "PetaLogix linux refdesign for xilinx ml605 (big endian)"; + mc->deprecation_reason = "big endian support is not tested"; +#else + mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)"; +#endif mc->init = petalogix_ml605_init; } diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index 43608c2dca..567aad47bf 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -181,9 +181,13 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine) static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc) { - mc->desc = "Xilinx ZynqMP PMU machine"; +#if TARGET_BIG_ENDIAN + mc->desc = "Xilinx ZynqMP PMU machine (big endian)"; + mc->deprecation_reason = "big endian support is not tested"; +#else + mc->desc = "Xilinx ZynqMP PMU machine (little endian)"; +#endif mc->init = xlnx_zynqmp_pmu_init; } DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init) - From c36ec3a9655f53a8cb21e9465f439a90ea9f1fc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 24 Sep 2024 23:58:19 +0200 Subject: [PATCH 03/29] hw/microblaze/s3adsp1800: Explicit CPU endianness MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit By default the machine's CPU endianness is 'big' order ('little-endian' property set to %false). This corresponds to the default when this machine was added; see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp MMU linux ref-design." and 72b675caacf "microblaze: Hook into the build-system." which added: [ "$target_cpu" = "microblaze" ] && target_bigendian=yes Later commit 877fdc12b1a ("microblaze: Allow targeting little-endian mb") added little-endian support, forgetting to set the CPU endianness to little-endian. Not an issue since this property was never used, but we will use it soon, so explicit the endianness to get the expected behavior. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.22564-4-philmd@linaro.org> --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index dad46bd7f9..37e9a05a62 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -71,6 +71,8 @@ petalogix_s3adsp1800_init(MachineState *machine) cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); + object_property_set_bool(OBJECT(cpu), "little-endian", + !TARGET_BIG_ENDIAN, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ From 1311b1b6e2b2eede53d6e81a1beed9d8f18e56f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 25 Sep 2024 23:16:51 +0200 Subject: [PATCH 04/29] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The machine datasheet mentions the GPIO device as 'xps_gpio'. Rename it accordingly to easily find its documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.22564-5-philmd@linaro.org> --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 37e9a05a62..581b0411e2 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -124,7 +124,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); - create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000); + create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); microblaze_load_kernel(cpu, ddr_base, ram_size, machine->initrd_filename, From 3f976457eaf12938b5b496733bf62b4daa63c282 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 25 Sep 2024 21:39:14 +0200 Subject: [PATCH 05/29] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.22564-6-philmd@linaro.org> --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 581b0411e2..6c0f5c6c65 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,6 +55,9 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 +#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ + MACHINE_TYPE_NAME("petalogix-s3adsp1800") + static void petalogix_s3adsp1800_init(MachineState *machine) { @@ -132,11 +135,21 @@ petalogix_s3adsp1800_init(MachineState *machine) NULL); } -static void petalogix_s3adsp1800_machine_init(MachineClass *mc) +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init = petalogix_s3adsp1800_init; mc->is_default = true; } -DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init) +static const TypeInfo petalogix_s3adsp1800_machine_types[] = { + { + .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .parent = TYPE_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init, + }, +}; + +DEFINE_TYPES(petalogix_s3adsp1800_machine_types) From 6e64c8ef8c15e459ef2423bc0214537bbca6c50f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 30 Sep 2024 12:33:28 +0200 Subject: [PATCH 06/29] hw/core/machine: Add missing 'units.h' and 'error-report.h' headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include the missing "qemu/units.h" to fix when refactoring code: ../hw/core/machine.c:743:34: error: use of undeclared identifier 'MiB' 743 | mc->default_ram_size = 128 * MiB; | ^ ../hw/core/machine.c:750:44: error: use of undeclared identifier 'TiB' 750 | mc->smbios_memory_device_size = 2047 * TiB; | ^ and "qemu/error-report.h" to fix: ../hw/core/machine.c:1029:13: error: call to undeclared function 'error_report' [-Wimplicit-function-declaration] 1029 | error_report("NUMA node %" PRIu16 " is missing, use " | ^ ../hw/core/machine.c:1240:9: error: call to undeclared function 'warn_report' [-Wimplicit-function-declaration] 1240 | warn_report("CPU model %s is deprecated -- %s", | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20240930221900.59525-2-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/core/machine.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 901c64b042..fd3716b7df 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -11,10 +11,12 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qemu/accel.h" #include "sysemu/replay.h" #include "hw/boards.h" #include "hw/loader.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/qapi-visit-machine.h" #include "qemu/madvise.h" From 34230ce5a97b898a53032b958841e74fde0bdac1 Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Fri, 1 Nov 2024 16:33:23 +0800 Subject: [PATCH 07/29] i386/cpu: Don't enumerate the "invalid" CPU topology level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the follow-up change, the CPU topology enumeration will be moved to QAPI. And considerring "invalid" should not be exposed to QAPI as an unsettable item, so, as a preparation for future changes, remove "invalid" level from the current CPU topology enumeration structure and define it by a macro instead. Due to the removal of the enumeration of "invalid", bit 0 of CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid" level, but will start at the SMT level. Therefore, to honor this change, update the encoding rule for CPUID[0x1F]. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron Message-ID: <20241101083331.340178-2-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i386/topology.h | 3 ++- target/i386/cpu.c | 13 ++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce11..48b43edc5a 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; +#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX + /* * CPUTopoLevel is the general i386 topology hierarchical representation, * ordered by increasing hierarchical relationship. @@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo { * or AMD (CPUID[0x80000026]). */ enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, CPU_TOPO_LEVEL_SMT, CPU_TOPO_LEVEL_CORE, CPU_TOPO_LEVEL_MODULE, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3baa95481f..ca13cf66a7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -370,20 +370,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, uint32_t *ecx, uint32_t *edx) { X86CPU *cpu = env_archcpu(env); - unsigned long level, next_level; + unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; - assert(count + 1 < CPU_TOPO_LEVEL_MAX); + assert(count <= CPU_TOPO_LEVEL_PACKAGE); /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). + * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). */ - level = CPU_TOPO_LEVEL_INVALID; + level = CPU_TOPO_LEVEL_SMT; + base_level = level; for (int i = 0; i <= count; i++) { level = find_next_bit(env->avail_cpu_topo, CPU_TOPO_LEVEL_PACKAGE, - level + 1); + base_level); /* * CPUID[0x1f] doesn't explicitly encode the package level, @@ -394,6 +395,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, level = CPU_TOPO_LEVEL_INVALID; break; } + /* Search the next level. */ + base_level = level + 1; } if (level == CPU_TOPO_LEVEL_INVALID) { From e823ebe77d8f38b181a3c277d5dd9399748bf566 Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Fri, 1 Nov 2024 16:33:24 +0800 Subject: [PATCH 08/29] hw/core: Make CPU topology enumeration arch-agnostic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and socket. Also, enumerate additional topology levels for non-i386 arches, and add a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work with compatibility requirement of arch-specific cache topology models. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Acked-by: Philippe Mathieu-Daudé Message-ID: <20241101083331.340178-3-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/x86-common.c | 4 +- include/hw/i386/topology.h | 23 ++---- qapi/machine-common.json | 44 +++++++++++- target/i386/cpu.c | 144 ++++++++++++++++++------------------- target/i386/cpu.h | 4 +- 5 files changed, 123 insertions(+), 96 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index b86c38212e..bc360a9ea4 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (ms->smp.modules > 1) { env->nr_modules = ms->smp.modules; - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); } if (ms->smp.dies > 1) { env->nr_dies = ms->smp.dies; - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo); } /* diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 48b43edc5a..b2c8bf2de1 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). */ - +#include "qapi/qapi-types-machine-common.h" #include "qemu/bitops.h" /* @@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX - -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; +#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -213,8 +198,8 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, */ static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) { - return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || - test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); + return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) || + test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap); } #endif /* HW_I386_TOPOLOGY_H */ diff --git a/qapi/machine-common.json b/qapi/machine-common.json index b64e4895cf..1a5687fb99 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -5,7 +5,7 @@ # See the COPYING file in the top-level directory. ## -# = Machines S390 data types +# = Common machine types ## ## @@ -18,3 +18,45 @@ ## { 'enum': 'S390CpuEntitlement', 'data': [ 'auto', 'low', 'medium', 'high' ] } + +## +# @CpuTopologyLevel: +# +# An enumeration of CPU topology levels. +# +# @thread: thread level, which would also be called SMT level or +# logical processor level. The @threads option in +# SMPConfiguration is used to configure the topology of this +# level. +# +# @core: core level. The @cores option in SMPConfiguration is used +# to configure the topology of this level. +# +# @module: module level. The @modules option in SMPConfiguration is +# used to configure the topology of this level. +# +# @cluster: cluster level. The @clusters option in SMPConfiguration +# is used to configure the topology of this level. +# +# @die: die level. The @dies option in SMPConfiguration is used to +# configure the topology of this level. +# +# @socket: socket level, which would also be called package level. +# The @sockets option in SMPConfiguration is used to configure +# the topology of this level. +# +# @book: book level. The @books option in SMPConfiguration is used +# to configure the topology of this level. +# +# @drawer: drawer level. The @drawers option in SMPConfiguration is +# used to configure the topology of this level. +# +# @default: default level. Some architectures will have default +# topology settings (e.g., cache topology), and this special +# level means following the architecture-specific settings. +# +# Since: 9.2 +## +{ 'enum': 'CpuTopologyLevel', + 'data': [ 'thread', 'core', 'module', 'cluster', 'die', + 'socket', 'book', 'drawer', 'default' ] } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca13cf66a7..d46710a403 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -238,23 +238,23 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 0 /* Invalid value */) static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel share_level) + enum CpuTopologyLevel share_level) { uint32_t num_ids = 0; switch (share_level) { - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: num_ids = 1 << apicid_pkg_offset(topo_info); break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for THREAD and MODULE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -303,19 +303,19 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, } static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 1; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return topo_info->threads_per_core; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return topo_info->threads_per_core * topo_info->cores_per_module; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -325,18 +325,18 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, } static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return 0; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return apicid_core_offset(topo_info); - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return apicid_module_offset(topo_info); - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPOLOGY_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -344,18 +344,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return 0; } -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_INVALID: + case CPU_TOPOLOGY_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPOLOGY_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; - case CPU_TOPO_LEVEL_CORE: + case CPU_TOPOLOGY_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; - case CPU_TOPO_LEVEL_MODULE: + case CPU_TOPOLOGY_LEVEL_MODULE: return CPUID_1F_ECX_TOPO_LEVEL_MODULE; - case CPU_TOPO_LEVEL_DIE: + case CPU_TOPOLOGY_LEVEL_DIE: return CPUID_1F_ECX_TOPO_LEVEL_DIE; default: /* Other types are not supported in QEMU. */ @@ -373,17 +373,17 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, unsigned long level, base_level, next_level; uint32_t num_threads_next_level, offset_next_level; - assert(count <= CPU_TOPO_LEVEL_PACKAGE); + assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. - * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT). + * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). */ - level = CPU_TOPO_LEVEL_SMT; + level = CPU_TOPOLOGY_LEVEL_THREAD; base_level = level; for (int i = 0; i <= count; i++) { level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, base_level); /* @@ -391,20 +391,20 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, * and it just encodes the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level == CPU_TOPO_LEVEL_PACKAGE) { - level = CPU_TOPO_LEVEL_INVALID; + if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { + level = CPU_TOPOLOGY_LEVEL_INVALID; break; } /* Search the next level. */ base_level = level + 1; } - if (level == CPU_TOPO_LEVEL_INVALID) { + if (level == CPU_TOPOLOGY_LEVEL_INVALID) { num_threads_next_level = 0; offset_next_level = 0; } else { next_level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPOLOGY_LEVEL_SOCKET, level + 1); num_threads_next_level = num_threads_by_topo_level(topo_info, next_level); @@ -580,7 +580,7 @@ static CPUCacheInfo legacy_l1d_cache = { .sets = 64, .partitions = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -595,7 +595,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = { .partitions = 1, .lines_per_tag = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /* L1 instruction cache: */ @@ -609,7 +609,7 @@ static CPUCacheInfo legacy_l1i_cache = { .sets = 64, .partitions = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -624,7 +624,7 @@ static CPUCacheInfo legacy_l1i_cache_amd = { .partitions = 1, .lines_per_tag = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /* Level 2 unified cache: */ @@ -638,7 +638,7 @@ static CPUCacheInfo legacy_l2_cache = { .sets = 4096, .partitions = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -648,7 +648,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 = { .size = 2 * MiB, .line_size = 64, .associativity = 8, - .share_level = CPU_TOPO_LEVEL_INVALID, + .share_level = CPU_TOPOLOGY_LEVEL_INVALID, }; @@ -662,7 +662,7 @@ static CPUCacheInfo legacy_l2_cache_amd = { .associativity = 16, .sets = 512, .partitions = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }; /* Level 3 unified cache: */ @@ -678,7 +678,7 @@ static CPUCacheInfo legacy_l3_cache = { .self_init = true, .inclusive = true, .complex_indexing = true, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }; /* TLB definitions: */ @@ -2085,7 +2085,7 @@ static const CPUCaches epyc_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2098,7 +2098,7 @@ static const CPUCaches epyc_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2109,7 +2109,7 @@ static const CPUCaches epyc_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2123,7 +2123,7 @@ static const CPUCaches epyc_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = true, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2139,7 +2139,7 @@ static CPUCaches epyc_v4_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2152,7 +2152,7 @@ static CPUCaches epyc_v4_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2163,7 +2163,7 @@ static CPUCaches epyc_v4_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2177,7 +2177,7 @@ static CPUCaches epyc_v4_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = false, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2193,7 +2193,7 @@ static const CPUCaches epyc_rome_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2206,7 +2206,7 @@ static const CPUCaches epyc_rome_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2217,7 +2217,7 @@ static const CPUCaches epyc_rome_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2231,7 +2231,7 @@ static const CPUCaches epyc_rome_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = true, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2247,7 +2247,7 @@ static const CPUCaches epyc_rome_v3_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2260,7 +2260,7 @@ static const CPUCaches epyc_rome_v3_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2271,7 +2271,7 @@ static const CPUCaches epyc_rome_v3_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2285,7 +2285,7 @@ static const CPUCaches epyc_rome_v3_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = false, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2301,7 +2301,7 @@ static const CPUCaches epyc_milan_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2314,7 +2314,7 @@ static const CPUCaches epyc_milan_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2325,7 +2325,7 @@ static const CPUCaches epyc_milan_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2339,7 +2339,7 @@ static const CPUCaches epyc_milan_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = true, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2355,7 +2355,7 @@ static const CPUCaches epyc_milan_v2_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2368,7 +2368,7 @@ static const CPUCaches epyc_milan_v2_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2379,7 +2379,7 @@ static const CPUCaches epyc_milan_v2_cache_info = { .partitions = 1, .sets = 1024, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2393,7 +2393,7 @@ static const CPUCaches epyc_milan_v2_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = false, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -2409,7 +2409,7 @@ static const CPUCaches epyc_genoa_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l1i_cache = &(CPUCacheInfo) { .type = INSTRUCTION_CACHE, @@ -2422,7 +2422,7 @@ static const CPUCaches epyc_genoa_cache_info = { .lines_per_tag = 1, .self_init = 1, .no_invd_sharing = true, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l2_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2433,7 +2433,7 @@ static const CPUCaches epyc_genoa_cache_info = { .partitions = 1, .sets = 2048, .lines_per_tag = 1, - .share_level = CPU_TOPO_LEVEL_CORE, + .share_level = CPU_TOPOLOGY_LEVEL_CORE, }, .l3_cache = &(CPUCacheInfo) { .type = UNIFIED_CACHE, @@ -2447,7 +2447,7 @@ static const CPUCaches epyc_genoa_cache_info = { .self_init = true, .inclusive = true, .complex_indexing = false, - .share_level = CPU_TOPO_LEVEL_DIE, + .share_level = CPU_TOPOLOGY_LEVEL_DIE, }, }; @@ -6591,7 +6591,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* Share the cache at package level. */ *eax |= max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPOLOGY_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -8169,10 +8169,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_modules = 1; env->nr_dies = 1; - /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + /* thread, core and socket levels are set by default. */ + set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); } static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 59959b8b7a..00b23bc5d1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1716,7 +1716,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; + CpuTopologyLevel share_level; } CPUCacheInfo; @@ -2051,7 +2051,7 @@ typedef struct CPUArchState { unsigned nr_modules; /* Bitmap of available CPU topology levels for this CPU. */ - DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); + DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); } CPUX86State; struct kvm_msrs; From 4e88e7e3403df23a0fd7a95daad1f00da80bcf81 Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Fri, 1 Nov 2024 16:33:25 +0800 Subject: [PATCH 09/29] qapi/qom: Define cache enumeration and properties for machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to the physical topology than a default topology would be. * For ARM, QEMU can't get the cache topology information from the CPU registers, then user configuration is necessary. Additionally, the cache information is also needed for MPAM emulation (for TCG) to build the right PPTT. Define smp-cache related enumeration and properties in QAPI, so that user could configure cache properties for SMP system through -machine in the subsequent patch. Cache enumeration (CacheLevelAndType) is implemented as the combination of cache level (level 1/2/3) and cache type (data/instruction/unified). Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache with smp-cache object to add the basic cache topology support. Other kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be added directly into CacheLevelAndType if necessary. Cache properties (SmpCacheProperties) currently only contains cache topology information, and other cache properties can be added in it if necessary. Note, define cache topology based on CPU topology level with two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. With smp-cache QAPI support, add smp cache topology for machine by parsing the smp-cache object list. Also add the helper to access/update cache topology level of machine. Suggested-by: Daniel P. Berrange Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Message-ID: <20241101083331.340178-4-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/core/machine-smp.c | 37 +++++++++++++++++++++++++++++ hw/core/machine.c | 44 +++++++++++++++++++++++++++++++++++ include/hw/boards.h | 12 ++++++++++ qapi/machine-common.json | 50 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 143 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 5d8d7edcbd..c6d90cd6d4 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,6 +261,31 @@ void machine_parse_smp_config(MachineState *ms, } } +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp) +{ + const SmpCachePropertiesList *node; + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); + + for (node = caches; node; node = node->next) { + /* Prohibit users from repeating settings. */ + if (test_bit(node->value->cache, caches_bitmap)) { + error_setg(errp, + "Invalid cache properties: %s. " + "The cache properties are duplicated", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + machine_set_cache_topo_level(ms, node->value->cache, + node->value->topology); + set_bit(node->value->cache, caches_bitmap); + } + + return true; +} + unsigned int machine_topo_get_cores_per_socket(const MachineState *ms) { return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies; @@ -270,3 +295,15 @@ unsigned int machine_topo_get_threads_per_socket(const MachineState *ms) { return ms->smp.threads * machine_topo_get_cores_per_socket(ms); } + +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache) +{ + return ms->smp_cache.props[cache].topology; +} + +void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, + CpuTopologyLevel level) +{ + ms->smp_cache.props[cache].topology = level; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index fd3716b7df..e6c92faf73 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -907,6 +907,40 @@ static void machine_set_smp(Object *obj, Visitor *v, const char *name, machine_parse_smp_config(ms, config, errp); } +static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MachineState *ms = MACHINE(obj); + SmpCache *cache = &ms->smp_cache; + SmpCachePropertiesList *head = NULL; + SmpCachePropertiesList **tail = &head; + + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + SmpCacheProperties *node = g_new(SmpCacheProperties, 1); + + node->cache = cache->props[i].cache; + node->topology = cache->props[i].topology; + QAPI_LIST_APPEND(tail, node); + } + + visit_type_SmpCachePropertiesList(v, name, &head, errp); + qapi_free_SmpCachePropertiesList(head); +} + +static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MachineState *ms = MACHINE(obj); + SmpCachePropertiesList *caches; + + if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { + return; + } + + machine_parse_smp_cache(ms, caches, errp); + qapi_free_SmpCachePropertiesList(caches); +} + static void machine_get_boot(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1067,6 +1101,11 @@ static void machine_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "smp", "CPU topology"); + object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", + machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); + object_class_property_set_description(oc, "smp-cache", + "Cache properties list for SMP machine"); + object_class_property_add(oc, "phandle-start", "int", machine_get_phandle_start, machine_set_phandle_start, NULL, NULL); @@ -1205,6 +1244,11 @@ static void machine_initfn(Object *obj) ms->smp.cores = 1; ms->smp.threads = 1; + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + ms->smp_cache.props[i].cache = (CacheLevelAndType)i; + ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT; + } + machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); } diff --git a/include/hw/boards.h b/include/hw/boards.h index a8f001fd21..b3a8064ccc 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -44,8 +44,15 @@ void machine_set_cpu_numa_node(MachineState *machine, Error **errp); void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp); +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp); unsigned int machine_topo_get_cores_per_socket(const MachineState *ms); unsigned int machine_topo_get_threads_per_socket(const MachineState *ms); +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache); +void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, + CpuTopologyLevel level); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); /** @@ -371,6 +378,10 @@ typedef struct CpuTopology { unsigned int max_cpus; } CpuTopology; +typedef struct SmpCache { + SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX]; +} SmpCache; + /** * MachineState: */ @@ -421,6 +432,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + SmpCache smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; diff --git a/qapi/machine-common.json b/qapi/machine-common.json index 1a5687fb99..298e51f373 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -60,3 +60,53 @@ { 'enum': 'CpuTopologyLevel', 'data': [ 'thread', 'core', 'module', 'cluster', 'die', 'socket', 'book', 'drawer', 'default' ] } + +## +# @CacheLevelAndType: +# +# Caches a system may have. The enumeration value here is the +# combination of cache level and cache type. +# +# @l1d: L1 data cache. +# +# @l1i: L1 instruction cache. +# +# @l2: L2 (unified) cache. +# +# @l3: L3 (unified) cache +# +# Since: 9.2 +## +{ 'enum': 'CacheLevelAndType', + 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } + +## +# @SmpCacheProperties: +# +# Cache information for SMP system. +# +# @cache: Cache name, which is the combination of cache level +# and cache type. +# +# @topology: Cache topology level. It accepts the CPU topology +# enumeration as the parameter, i.e., CPUs in the same +# topology container share the same cache. +# +# Since: 9.2 +## +{ 'struct': 'SmpCacheProperties', + 'data': { + 'cache': 'CacheLevelAndType', + 'topology': 'CpuTopologyLevel' } } + +## +# @SmpCachePropertiesWrapper: +# +# List wrapper of SmpCacheProperties. +# +# @caches: the list of SmpCacheProperties. +# +# Since 9.2 +## +{ 'struct': 'SmpCachePropertiesWrapper', + 'data': { 'caches': ['SmpCacheProperties'] } } From f35c0221fef864e65db7641bb041c5f913e31475 Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Fri, 1 Nov 2024 16:33:26 +0800 Subject: [PATCH 10/29] hw/core: Check smp cache topology support for machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Message-ID: <20241101083331.340178-5-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/core/machine-smp.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 3 +++ 2 files changed, 44 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index c6d90cd6d4..ebb7a134a7 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,10 +261,32 @@ void machine_parse_smp_config(MachineState *ms, } } +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) || + (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) || + (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) || + (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + bool machine_parse_smp_cache(MachineState *ms, const SmpCachePropertiesList *caches, Error **errp) { + MachineClass *mc = MACHINE_GET_CLASS(ms); const SmpCachePropertiesList *node; DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); @@ -283,6 +305,25 @@ bool machine_parse_smp_cache(MachineState *ms, set_bit(node->value->cache, caches_bitmap); } + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + const SmpCacheProperties *props = &ms->smp_cache.props[i]; + + /* + * Reject non "default" topology level if the cache isn't + * supported by the machine. + */ + if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[props->cache]) { + error_setg(errp, + "%s cache topology not supported by this machine", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + if (!machine_check_topo_support(ms, props->topology, errp)) { + return false; + } + } return true; } diff --git a/include/hw/boards.h b/include/hw/boards.h index b3a8064ccc..edf1a8ca1c 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -153,6 +153,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -162,6 +164,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; } SMPCompatProps; /** From 07995a46bae9d2ec0971b435834c60a4df84b03f Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Fri, 1 Nov 2024 16:33:27 +0800 Subject: [PATCH 11/29] hw/core: Add a helper to check the cache topology level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, we have no way to expose the arch-specific default cache model because the cache model is sometimes related to the CPU model (e.g., i386). Since the user might configure "default" level, any comparison with "default" is meaningless before the machine knows the specific level that "default" refers to. We can only check the correctness of the cache topology after the arch loads the user-configured cache model from MachineState.smp_cache and consumes the special "default" level by replacing it with the specific level. Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron Message-ID: <20241101083331.340178-6-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/core/machine-smp.c | 48 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 1 + 2 files changed, 49 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index ebb7a134a7..640b2114b4 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -348,3 +348,51 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, { ms->smp_cache.props[cache].topology = level; } + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SmpCache *smp_cache, + CacheLevelAndType cache1, + CacheLevelAndType cache2) +{ + /* + * Before comparing, the "default" topology level should be replaced + * with the specific level. + */ + assert(smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT); + + return smp_cache->props[cache1].topology > smp_cache->props[cache2].topology; +} + +/* + * Currently, we have no way to expose the arch-specific default cache model + * because the cache model is sometimes related to the CPU model (e.g., i386). + * + * We can only check the correctness of the cache topology after the arch loads + * the user-configured cache model from MachineState and consumes the special + * "default" level by replacing it with the specific level. + */ +bool machine_check_smp_cache(const MachineState *ms, Error **errp) +{ + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D, + CACHE_LEVEL_AND_TYPE_L2) || + smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I, + CACHE_LEVEL_AND_TYPE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cache"); + return false; + } + + if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2, + CACHE_LEVEL_AND_TYPE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cache"); + return false; + } + + return true; +} diff --git a/include/hw/boards.h b/include/hw/boards.h index edf1a8ca1c..36fbb9b59d 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -53,6 +53,7 @@ CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, CacheLevelAndType cache); void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, CpuTopologyLevel level); +bool machine_check_smp_cache(const MachineState *ms, Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); /** From c620b4ee92ed3664a3d98e0fbb0b651e19fba5b6 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:49 +0100 Subject: [PATCH 12/29] hw/ppc/e500: Prefer QOM cast MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 6433348072..060db36dbc 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -1021,7 +1021,7 @@ void ppce500_init(MachineState *machine) sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, sysbus_mmio_get_region(s, 0)); - i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); + i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c")); i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); /* eSDHC */ @@ -1070,7 +1070,7 @@ void ppce500_init(MachineState *machine) memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, sysbus_mmio_get_region(s, 0)); - pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); + pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); if (!pci_bus) printf("couldn't create PCI controller!\n"); From 2a309354ac5decf78763c9de999bfb42c8612069 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:50 +0100 Subject: [PATCH 13/29] hw/ppc/e500: Remove unused "irqs" parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 060db36dbc..d4d3a92796 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -829,7 +829,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, } static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, - IrqLines *irqs, Error **errp) + Error **errp) { #ifdef CONFIG_KVM DeviceState *dev; @@ -869,7 +869,7 @@ static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, Error *err = NULL; if (kvm_kernel_irqchip_allowed()) { - dev = ppce500_init_mpic_kvm(pmc, irqs, &err); + dev = ppce500_init_mpic_kvm(pmc, &err); } if (kvm_kernel_irqchip_required() && !dev) { error_reportf_err(err, From b5d65592d931d07d4f4bcb915d018ec9598058b4 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:51 +0100 Subject: [PATCH 14/29] hw/ppc/e500: Add missing device tree properties to i2c controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When compiling a decompiled device tree blob created with dumpdtb, dtc complains with: /soc@e0000000/i2c@3000: incorrect #address-cells for I2C bus /soc@e0000000/i2c@3000: incorrect #size-cells for I2C bus Fix this by adding the missing device tree properties. Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index d4d3a92796..46261223f3 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -203,6 +203,8 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); + qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1); qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); g_free(i2c); From 6b0cc658284b24e2d6d608a8e6150aa9b6747d9f Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:56 +0100 Subject: [PATCH 15/29] hw/ppc/mpc8544_guts: Populate POR PLL ratio status register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Populate this read-only register with some arbitrary values which avoids U-Boot's get_clocks() to hang(). Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-11-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/mpc8544_guts.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index e3540b0281..c02b34ccde 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -29,6 +29,12 @@ #define MPC8544_GUTS_RSTCR_RESET 0x02 #define MPC8544_GUTS_ADDR_PORPLLSR 0x00 +REG32(GUTS_PORPLLSR, 0x00) + FIELD(GUTS_PORPLLSR, E500_1_RATIO, 24, 6) + FIELD(GUTS_PORPLLSR, E500_0_RATIO, 16, 6) + FIELD(GUTS_PORPLLSR, DDR_RATIO, 9, 5) + FIELD(GUTS_PORPLLSR, PLAT_RATIO, 1, 5) + #define MPC8544_GUTS_ADDR_PORBMSR 0x04 #define MPC8544_GUTS_ADDR_PORIMPSCR 0x08 #define MPC8544_GUTS_ADDR_PORDEVSR 0x0C @@ -75,6 +81,12 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { + case MPC8544_GUTS_ADDR_PORPLLSR: + value = FIELD_DP32(value, GUTS_PORPLLSR, E500_1_RATIO, 6); /* 3:1 */ + value = FIELD_DP32(value, GUTS_PORPLLSR, E500_0_RATIO, 6); /* 3:1 */ + value = FIELD_DP32(value, GUTS_PORPLLSR, DDR_RATIO, 12); /* 12:1 */ + value = FIELD_DP32(value, GUTS_PORPLLSR, PLAT_RATIO, 6); /* 6:1 */ + break; case MPC8544_GUTS_ADDR_PVR: value = env->spr[SPR_PVR]; break; From 1d97f16edb4e6ff38488194ce9cd34e67743b402 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:57 +0100 Subject: [PATCH 16/29] hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Acked-by: Corey Minyard Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/mpc_i2c.c | 9 +++++---- hw/i2c/trace-events | 5 +++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 2467d1a9aa..3d79c15653 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -24,6 +24,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" +#include "trace.h" /* #define DEBUG_I2C */ @@ -224,8 +225,8 @@ static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__, - addr, value); + trace_mpc_i2c_read(addr, value); + return (uint64_t)value; } @@ -234,8 +235,8 @@ static void mpc_i2c_write(void *opaque, hwaddr addr, { MPCI2CState *s = opaque; - DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__, - addr, value); + trace_mpc_i2c_write(addr, value); + switch (addr) { case MPC_I2C_ADR: s->adr = value & CADR_MASK; diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 6900e06eda..f708a7ace1 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -35,6 +35,11 @@ aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t va aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x" aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x" +# mpc_i2c.c + +mpc_i2c_read(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] -> 0x%02" PRIx32 +mpc_i2c_write(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] <- 0x%02" PRIx32 + # npcm7xx_smbus.c npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" From 21b1ee7691693fc84d6d4e11a1533112f629e97a Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:58 +0100 Subject: [PATCH 17/29] hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Acked-by: Corey Minyard Message-ID: <20241103133412.73536-13-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/mpc_i2c.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 3d79c15653..913d044ac1 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" -#include "qemu/module.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" @@ -345,16 +344,13 @@ static void mpc_i2c_class_init(ObjectClass *klass, void *data) dc->desc = "MPC I2C Controller"; } -static const TypeInfo mpc_i2c_type_info = { - .name = TYPE_MPC_I2C, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(MPCI2CState), - .class_init = mpc_i2c_class_init, +static const TypeInfo mpc_i2c_types[] = { + { + .name = TYPE_MPC_I2C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MPCI2CState), + .class_init = mpc_i2c_class_init, + }, }; -static void mpc_i2c_register_types(void) -{ - type_register_static(&mpc_i2c_type_info); -} - -type_init(mpc_i2c_register_types) +DEFINE_TYPES(mpc_i2c_types) From f03d53f9e0ac10a011957c4b3fff01ec4f620a27 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:33:59 +0100 Subject: [PATCH 18/29] hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prefer a macro rather than a string literal when instantiaging device models. Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/ppce500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 95b983b2b3..5a4a924a2f 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -475,7 +475,7 @@ static void e500_pcihost_realize(DeviceState *dev, Error **errp) address_space_init(&s->bm_as, &s->bm, "pci-bm"); pci_setup_iommu(b, &ppce500_iommu_ops, s); - pci_create_simple(b, 0, "e500-host-bridge"); + pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE); memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, From ab22a14dc03a9d73479203bd1ae9c0522b8a4898 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:00 +0100 Subject: [PATCH 19/29] hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-15-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/ppce500.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 5a4a924a2f..b70631045a 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -22,7 +22,6 @@ #include "hw/pci/pci_device.h" #include "hw/pci/pci_host.h" #include "qemu/bswap.h" -#include "qemu/module.h" #include "hw/pci-host/ppce500.h" #include "qom/object.h" @@ -508,17 +507,6 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; } -static const TypeInfo e500_host_bridge_info = { - .name = TYPE_PPC_E500_PCI_BRIDGE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PPCE500PCIBridgeState), - .class_init = e500_host_bridge_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - static Property pcihost_properties[] = { DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), @@ -535,17 +523,23 @@ static void e500_pcihost_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_ppce500_pci; } -static const TypeInfo e500_pcihost_info = { - .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, - .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(PPCE500PCIState), - .class_init = e500_pcihost_class_init, +static const TypeInfo e500_pci_types[] = { + { + .name = TYPE_PPC_E500_PCI_BRIDGE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PPCE500PCIBridgeState), + .class_init = e500_host_bridge_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, + }, + { + .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, + .parent = TYPE_PCI_HOST_BRIDGE, + .instance_size = sizeof(PPCE500PCIState), + .class_init = e500_pcihost_class_init, + }, }; -static void e500_pci_register_types(void) -{ - type_register_static(&e500_pcihost_info); - type_register_static(&e500_host_bridge_info); -} - -type_init(e500_pci_register_types) +DEFINE_TYPES(e500_pci_types) From 65a12bb57246a1fcadb00b544946af0cf5ed8127 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:01 +0100 Subject: [PATCH 20/29] hw/net/fsl_etsec/miim: Reuse MII constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of defining redundant constants and using magic numbers reuse the existing MII constants. Signed-off-by: Bernhard Beschow cc: Akihiko Odaki Reviewed-by: Akihiko Odaki Message-ID: <20241103133412.73536-16-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/miim.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/hw/net/fsl_etsec/miim.c b/hw/net/fsl_etsec/miim.c index b48d2cb57b..4e9169907a 100644 --- a/hw/net/fsl_etsec/miim.c +++ b/hw/net/fsl_etsec/miim.c @@ -29,13 +29,6 @@ /* #define DEBUG_MIIM */ -#define MIIM_CONTROL 0 -#define MIIM_STATUS 1 -#define MIIM_PHY_ID_1 2 -#define MIIM_PHY_ID_2 3 -#define MIIM_T2_STATUS 10 -#define MIIM_EXT_STATUS 15 - static void miim_read_cycle(eTSEC *etsec) { uint8_t phy; @@ -47,14 +40,14 @@ static void miim_read_cycle(eTSEC *etsec) addr = etsec->regs[MIIMADD].value & 0x1F; switch (addr) { - case MIIM_CONTROL: + case MII_BMCR: value = etsec->phy_control; break; - case MIIM_STATUS: + case MII_BMSR: value = etsec->phy_status; break; - case MIIM_T2_STATUS: - value = 0x1800; /* Local and remote receivers OK */ + case MII_STAT1000: + value = MII_STAT1000_LOK | MII_STAT1000_ROK; break; default: value = 0x0; @@ -84,8 +77,8 @@ static void miim_write_cycle(eTSEC *etsec) #endif switch (addr) { - case MIIM_CONTROL: - etsec->phy_control = value & ~(0x8100); + case MII_BMCR: + etsec->phy_control = value & ~(MII_BMCR_RESET | MII_BMCR_FD); break; default: break; From 59e0f9902425f88c7e54b40db29a72eaad73c509 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:02 +0100 Subject: [PATCH 21/29] hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-17-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index 3fdd16ef2e..d8076e7be4 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -36,7 +36,6 @@ #include "registers.h" #include "qapi/error.h" #include "qemu/log.h" -#include "qemu/module.h" /* #define HEX_DUMP */ /* #define DEBUG_REGISTER */ @@ -431,17 +430,14 @@ static void etsec_class_init(ObjectClass *klass, void *data) dc->user_creatable = true; } -static const TypeInfo etsec_info = { - .name = TYPE_ETSEC_COMMON, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(eTSEC), - .class_init = etsec_class_init, - .instance_init = etsec_instance_init, +static const TypeInfo etsec_types[] = { + { + .name = TYPE_ETSEC_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(eTSEC), + .class_init = etsec_class_init, + .instance_init = etsec_instance_init, + }, }; -static void etsec_register_types(void) -{ - type_register_static(&etsec_info); -} - -type_init(etsec_register_types) +DEFINE_TYPES(etsec_types) From c267da0e271947d59db9524a3e51fdfd860ef7ef Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:03 +0100 Subject: [PATCH 22/29] hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-18-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/gpio/mpc8xxx.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/hw/gpio/mpc8xxx.c b/hw/gpio/mpc8xxx.c index 63b7a5c881..a3c1d2fbf4 100644 --- a/hw/gpio/mpc8xxx.c +++ b/hw/gpio/mpc8xxx.c @@ -23,7 +23,6 @@ #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "qemu/module.h" #include "qom/object.h" #define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio" @@ -208,17 +207,14 @@ static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data) device_class_set_legacy_reset(dc, mpc8xxx_gpio_reset); } -static const TypeInfo mpc8xxx_gpio_info = { - .name = TYPE_MPC8XXX_GPIO, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(MPC8XXXGPIOState), - .instance_init = mpc8xxx_gpio_initfn, - .class_init = mpc8xxx_gpio_class_init, +static const TypeInfo mpc8xxx_gpio_types[] = { + { + .name = TYPE_MPC8XXX_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MPC8XXXGPIOState), + .instance_init = mpc8xxx_gpio_initfn, + .class_init = mpc8xxx_gpio_class_init, + }, }; -static void mpc8xxx_gpio_register_types(void) -{ - type_register_static(&mpc8xxx_gpio_info); -} - -type_init(mpc8xxx_gpio_register_types) +DEFINE_TYPES(mpc8xxx_gpio_types) From 0ab117f0846f415b4eb4822e07db438375a9e210 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:04 +0100 Subject: [PATCH 23/29] hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-19-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/mpc8544_guts.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index c02b34ccde..e3c51458e6 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu/module.h" #include "qemu/log.h" #include "sysemu/runstate.h" #include "cpu.h" @@ -141,16 +140,13 @@ static void mpc8544_guts_initfn(Object *obj) sysbus_init_mmio(d, &s->iomem); } -static const TypeInfo mpc8544_guts_info = { - .name = TYPE_MPC8544_GUTS, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(GutsState), - .instance_init = mpc8544_guts_initfn, +static const TypeInfo mpc8544_guts_types[] = { + { + .name = TYPE_MPC8544_GUTS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GutsState), + .instance_init = mpc8544_guts_initfn, + }, }; -static void mpc8544_guts_register_types(void) -{ - type_register_static(&mpc8544_guts_info); -} - -type_init(mpc8544_guts_register_types) +DEFINE_TYPES(mpc8544_guts_types) From 911f4dd85b298e8c366f450129fcb62b33eb3a0c Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:06 +0100 Subject: [PATCH 24/29] hw/sd/sdhci: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-21-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 62 +++++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..dbe5c2340c 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -37,7 +37,6 @@ #include "migration/vmstate.h" #include "sdhci-internal.h" #include "qemu/log.h" -#include "qemu/module.h" #include "trace.h" #include "qom/object.h" @@ -1598,15 +1597,6 @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) sdhci_common_class_init(klass, data); } -static const TypeInfo sdhci_sysbus_info = { - .name = TYPE_SYSBUS_SDHCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SDHCIState), - .instance_init = sdhci_sysbus_init, - .instance_finalize = sdhci_sysbus_finalize, - .class_init = sdhci_sysbus_class_init, -}; - /* --- qdev bus master --- */ static void sdhci_bus_class_init(ObjectClass *klass, void *data) @@ -1617,13 +1607,6 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -static const TypeInfo sdhci_bus_info = { - .name = TYPE_SDHCI_BUS, - .parent = TYPE_SD_BUS, - .instance_size = sizeof(SDBus), - .class_init = sdhci_bus_class_init, -}; - /* --- qdev i.MX eSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1882,12 +1865,6 @@ static void imx_usdhc_init(Object *obj) s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; } -static const TypeInfo imx_usdhc_info = { - .name = TYPE_IMX_USDHC, - .parent = TYPE_SYSBUS_SDHCI, - .instance_init = imx_usdhc_init, -}; - /* --- qdev Samsung s3c --- */ #define S3C_SDHCI_CONTROL2 0x80 @@ -1946,18 +1923,31 @@ static void sdhci_s3c_init(Object *obj) s->io_ops = &sdhci_s3c_mmio_ops; } -static const TypeInfo sdhci_s3c_info = { - .name = TYPE_S3C_SDHCI , - .parent = TYPE_SYSBUS_SDHCI, - .instance_init = sdhci_s3c_init, +static const TypeInfo sdhci_types[] = { + { + .name = TYPE_SDHCI_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = sdhci_bus_class_init, + }, + { + .name = TYPE_SYSBUS_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SDHCIState), + .instance_init = sdhci_sysbus_init, + .instance_finalize = sdhci_sysbus_finalize, + .class_init = sdhci_sysbus_class_init, + }, + { + .name = TYPE_IMX_USDHC, + .parent = TYPE_SYSBUS_SDHCI, + .instance_init = imx_usdhc_init, + }, + { + .name = TYPE_S3C_SDHCI, + .parent = TYPE_SYSBUS_SDHCI, + .instance_init = sdhci_s3c_init, + }, }; -static void sdhci_register_types(void) -{ - type_register_static(&sdhci_sysbus_info); - type_register_static(&sdhci_bus_info); - type_register_static(&imx_usdhc_info); - type_register_static(&sdhci_s3c_info); -} - -type_init(sdhci_register_types) +DEFINE_TYPES(sdhci_types) From 2b88cd1782f9182e761f4664d243af2086e6361d Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:07 +0100 Subject: [PATCH 25/29] hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Reviewed-by: Kevin Wolf Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-22-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 7b6ec64442..21a81b44f0 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -47,7 +47,6 @@ #include "qemu/bitops.h" #include "qemu/host-utils.h" #include "qemu/log.h" -#include "qemu/module.h" #include "qemu/option.h" #include "hw/sysbus.h" #include "migration/vmstate.h" @@ -947,20 +946,16 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } - -static const TypeInfo pflash_cfi01_info = { - .name = TYPE_PFLASH_CFI01, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(PFlashCFI01), - .class_init = pflash_cfi01_class_init, +static const TypeInfo pflash_cfi01_types[] = { + { + .name = TYPE_PFLASH_CFI01, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PFlashCFI01), + .class_init = pflash_cfi01_class_init, + }, }; -static void pflash_cfi01_register_types(void) -{ - type_register_static(&pflash_cfi01_info); -} - -type_init(pflash_cfi01_register_types) +DEFINE_TYPES(pflash_cfi01_types) PFlashCFI01 *pflash_cfi01_register(hwaddr base, const char *name, From 34965e8920ba99f80ffcd369bf3cdfbbe196fb8b Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:08 +0100 Subject: [PATCH 26/29] hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Acked-by: Corey Minyard Message-ID: <20241103133412.73536-23-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/smbus_eeprom.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c index 9e62c27a1a..e3e96d4a2d 100644 --- a/hw/i2c/smbus_eeprom.c +++ b/hw/i2c/smbus_eeprom.c @@ -151,19 +151,16 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) dc->user_creatable = false; } -static const TypeInfo smbus_eeprom_info = { - .name = TYPE_SMBUS_EEPROM, - .parent = TYPE_SMBUS_DEVICE, - .instance_size = sizeof(SMBusEEPROMDevice), - .class_init = smbus_eeprom_class_initfn, +static const TypeInfo smbus_eeprom_types[] = { + { + .name = TYPE_SMBUS_EEPROM, + .parent = TYPE_SMBUS_DEVICE, + .instance_size = sizeof(SMBusEEPROMDevice), + .class_init = smbus_eeprom_class_initfn, + }, }; -static void smbus_eeprom_register_types(void) -{ - type_register_static(&smbus_eeprom_info); -} - -type_init(smbus_eeprom_register_types) +DEFINE_TYPES(smbus_eeprom_types) void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) { From 7a5f6bad7a139cdeec130f32af020ff21c6ef37a Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:09 +0100 Subject: [PATCH 27/29] hw/rtc/ds1338: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-24-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/rtc/ds1338.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index a5fe221418..13472c5670 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -14,7 +14,6 @@ #include "hw/i2c/i2c.h" #include "migration/vmstate.h" #include "qemu/bcd.h" -#include "qemu/module.h" #include "qom/object.h" #include "sysemu/rtc.h" @@ -227,16 +226,13 @@ static void ds1338_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_ds1338; } -static const TypeInfo ds1338_info = { - .name = TYPE_DS1338, - .parent = TYPE_I2C_SLAVE, - .instance_size = sizeof(DS1338State), - .class_init = ds1338_class_init, +static const TypeInfo ds1338_types[] = { + { + .name = TYPE_DS1338, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(DS1338State), + .class_init = ds1338_class_init, + }, }; -static void ds1338_register_types(void) -{ - type_register_static(&ds1338_info); -} - -type_init(ds1338_register_types) +DEFINE_TYPES(ds1338_types) From 887c510daa54d6e2b8ba7c94a21c7b76ca95b24d Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Sun, 3 Nov 2024 14:34:10 +0100 Subject: [PATCH 28/29] hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The naming of the TypeInfo array is inspired by hcd-ohci-sysbus. Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-25-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/hcd-ehci-sysbus.c | 118 +++++++++++++++++---------------------- 1 file changed, 50 insertions(+), 68 deletions(-) diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 2b1652f7a8..eb7df93ac2 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -19,7 +19,6 @@ #include "hw/qdev-properties.h" #include "hw/usb/hcd-ehci.h" #include "migration/vmstate.h" -#include "qemu/module.h" static const VMStateDescription vmstate_ehci_sysbus = { .name = "ehci-sysbus", @@ -97,17 +96,6 @@ static void ehci_sysbus_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_type_info = { - .name = TYPE_SYS_BUS_EHCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(EHCISysBusState), - .instance_init = ehci_sysbus_init, - .instance_finalize = ehci_sysbus_finalize, - .abstract = true, - .class_init = ehci_sysbus_class_init, - .class_size = sizeof(SysBusEHCIClass), -}; - static void ehci_platform_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -118,12 +106,6 @@ static void ehci_platform_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_platform_type_info = { - .name = TYPE_PLATFORM_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_platform_class_init, -}; - static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -134,12 +116,6 @@ static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_exynos4210_type_info = { - .name = TYPE_EXYNOS4210_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_exynos4210_class_init, -}; - static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -150,12 +126,6 @@ static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_aw_h3_type_info = { - .name = TYPE_AW_H3_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_aw_h3_class_init, -}; - static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -168,12 +138,6 @@ static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_npcm7xx_type_info = { - .name = TYPE_NPCM7XX_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_npcm7xx_class_init, -}; - static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -184,12 +148,6 @@ static void ehci_tegra2_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_tegra2_type_info = { - .name = TYPE_TEGRA2_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_tegra2_class_init, -}; - static void ehci_ppc4xx_init(Object *o) { EHCISysBusState *s = SYS_BUS_EHCI(o); @@ -207,13 +165,6 @@ static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_ppc4xx_type_info = { - .name = TYPE_PPC4xx_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_ppc4xx_class_init, - .instance_init = ehci_ppc4xx_init, -}; - /* * Faraday FUSBH200 USB 2.0 EHCI */ @@ -282,24 +233,55 @@ static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_USB, dc->categories); } -static const TypeInfo ehci_fusbh200_type_info = { - .name = TYPE_FUSBH200_EHCI, - .parent = TYPE_SYS_BUS_EHCI, - .instance_size = sizeof(FUSBH200EHCIState), - .instance_init = fusbh200_ehci_init, - .class_init = fusbh200_ehci_class_init, +static const TypeInfo ehci_sysbus_types[] = { + { + .name = TYPE_SYS_BUS_EHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(EHCISysBusState), + .instance_init = ehci_sysbus_init, + .instance_finalize = ehci_sysbus_finalize, + .abstract = true, + .class_init = ehci_sysbus_class_init, + .class_size = sizeof(SysBusEHCIClass), + }, + { + .name = TYPE_PLATFORM_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_platform_class_init, + }, + { + .name = TYPE_EXYNOS4210_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_exynos4210_class_init, + }, + { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, + }, + { + .name = TYPE_NPCM7XX_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_npcm7xx_class_init, + }, + { + .name = TYPE_TEGRA2_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_tegra2_class_init, + }, + { + .name = TYPE_PPC4xx_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_ppc4xx_class_init, + .instance_init = ehci_ppc4xx_init, + }, + { + .name = TYPE_FUSBH200_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .instance_size = sizeof(FUSBH200EHCIState), + .instance_init = fusbh200_ehci_init, + .class_init = fusbh200_ehci_class_init, + }, }; -static void ehci_sysbus_register_types(void) -{ - type_register_static(&ehci_type_info); - type_register_static(&ehci_platform_type_info); - type_register_static(&ehci_exynos4210_type_info); - type_register_static(&ehci_aw_h3_type_info); - type_register_static(&ehci_npcm7xx_type_info); - type_register_static(&ehci_tegra2_type_info); - type_register_static(&ehci_ppc4xx_type_info); - type_register_static(&ehci_fusbh200_type_info); -} - -type_init(ehci_sysbus_register_types) +DEFINE_TYPES(ehci_sysbus_types) From d37eede7a8e6ff33d21aacb41a68e63e8ffa1d60 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Mon, 4 Nov 2024 14:22:25 -0800 Subject: [PATCH 29/29] hw/riscv/iommu: fix build error with clang MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduced in 0c54acb8243, "hw/riscv: add RISC-V IOMMU base emulation". ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) | ^ D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here 217 | _pext_u64(unsigned long long __X, unsigned long long __Y) | ^ After a conversation on the mailing list, it was decided to rename and add a comment for this function. Signed-off-by: Pierrick Bouvier Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20241104222225.1523751-1-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index feb650549a..12f01a75f5 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -183,8 +183,25 @@ static void riscv_iommu_pri(RISCVIOMMUState *s, } } -/* Portable implementation of pext_u64, bit-mask extraction. */ -static uint64_t _pext_u64(uint64_t val, uint64_t ext) +/* + * Discards all bits from 'val' whose matching bits in the same + * positions in the mask 'ext' are zeros, and packs the remaining + * bits from 'val' contiguously at the least-significant end of the + * result, keeping the same bit order as 'val' and filling any + * other bits at the most-significant end of the result with zeros. + * + * For example, for the following 'val' and 'ext', the return 'ret' + * will be: + * + * val = a b c d e f g h + * ext = 1 0 1 0 0 1 1 0 + * ret = 0 0 0 0 a c f g + * + * This function, taken from the riscv-iommu 1.0 spec, section 2.3.3 + * "Process to translate addresses of MSIs", is similar to bit manip + * function PEXT (Parallel bits extract) from x86. + */ +static uint64_t riscv_iommu_pext_u64(uint64_t val, uint64_t ext) { uint64_t ret = 0; uint64_t rot = 1; @@ -528,7 +545,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s, int cause; /* Interrupt File Number */ - intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); + intn = riscv_iommu_pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); if (intn >= 256) { /* Interrupt file number out of range */ res = MEMTX_ACCESS_ERROR;