target-lm32: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPULM32State/g" target-lm32/*.[hc] sed -i "s/#define CPULM32State/#define CPUState/" target-lm32/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
317ac6201a
commit
6393c08de2
@ -36,7 +36,7 @@ typedef struct CPULM32State CPULM32State;
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#define NB_MMU_MODES 1
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#define TARGET_PAGE_BITS 12
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static inline int cpu_mmu_index(CPUState *env)
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static inline int cpu_mmu_index(CPULM32State *env)
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{
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return 0;
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}
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@ -185,18 +185,18 @@ typedef struct CPULM32State {
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} CPULM32State;
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CPUState *cpu_lm32_init(const char *cpu_model);
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CPULM32State *cpu_lm32_init(const char *cpu_model);
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void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
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int cpu_lm32_exec(CPUState *s);
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void cpu_lm32_close(CPUState *s);
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void do_interrupt(CPUState *env);
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int cpu_lm32_exec(CPULM32State *s);
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void cpu_lm32_close(CPULM32State *s);
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void do_interrupt(CPULM32State *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_lm32_signal_handler(int host_signum, void *pinfo,
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void *puc);
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void lm32_translate_init(void);
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void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
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#define cpu_list cpu_lm32_list
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#define cpu_init cpu_lm32_init
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@ -206,12 +206,12 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
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#define CPU_SAVE_VERSION 1
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int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
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int mmu_idx);
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#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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static inline void cpu_clone_regs(CPULM32State *env, target_ulong newsp)
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{
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if (newsp) {
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env->regs[R_SP] = newsp;
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@ -220,23 +220,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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}
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#endif
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static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
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static inline void cpu_set_tls(CPULM32State *env, target_ulong newtls)
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{
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}
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static inline int cpu_interrupts_enabled(CPUState *env)
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static inline int cpu_interrupts_enabled(CPULM32State *env)
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{
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return env->ie & IE_IE;
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}
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#include "cpu-all.h"
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static inline target_ulong cpu_get_pc(CPUState *env)
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static inline target_ulong cpu_get_pc(CPULM32State *env)
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{
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return env->pc;
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}
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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@ -244,14 +244,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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*flags = 0;
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}
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static inline bool cpu_has_work(CPUState *env)
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static inline bool cpu_has_work(CPULM32State *env)
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{
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return env->interrupt_request & CPU_INTERRUPT_HARD;
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}
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#include "exec-all.h"
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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}
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@ -20,7 +20,7 @@
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#include "cpu.h"
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#include "host-utils.h"
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int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
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int mmu_idx)
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{
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int prot;
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@ -37,12 +37,12 @@ int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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return 0;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
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{
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return addr & TARGET_PAGE_MASK;
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}
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void do_interrupt(CPUState *env)
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void do_interrupt(CPULM32State *env)
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{
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%x type=%x\n", env->pc, env->exception_index);
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@ -192,9 +192,9 @@ static uint32_t cfg_by_def(const LM32Def *def)
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return cfg;
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}
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CPUState *cpu_lm32_init(const char *cpu_model)
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CPULM32State *cpu_lm32_init(const char *cpu_model)
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{
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CPUState *env;
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CPULM32State *env;
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const LM32Def *def;
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static int tcg_initialized;
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@ -203,7 +203,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
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return NULL;
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}
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env = g_malloc0(sizeof(CPUState));
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env = g_malloc0(sizeof(CPULM32State));
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env->features = def->features;
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env->num_bps = def->num_breakpoints;
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@ -226,7 +226,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
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/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
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* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
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* 0x80000000-0xffffffff is not cached and used to access IO devices. */
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void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
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{
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if (value) {
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env->flags |= LM32_FLAG_IGNORE_MSB;
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@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
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}
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}
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void cpu_state_reset(CPUState *env)
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void cpu_state_reset(CPULM32State *env)
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{
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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@ -7,17 +7,17 @@ static const VMStateDescription vmstate_cpu = {
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, CPUState, 32),
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VMSTATE_UINT32(pc, CPUState),
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VMSTATE_UINT32(ie, CPUState),
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VMSTATE_UINT32(icc, CPUState),
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VMSTATE_UINT32(dcc, CPUState),
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VMSTATE_UINT32(cc, CPUState),
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VMSTATE_UINT32(eba, CPUState),
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VMSTATE_UINT32(dc, CPUState),
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VMSTATE_UINT32(deba, CPUState),
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VMSTATE_UINT32_ARRAY(bp, CPUState, 4),
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VMSTATE_UINT32_ARRAY(wp, CPUState, 4),
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VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
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VMSTATE_UINT32(pc, CPULM32State),
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VMSTATE_UINT32(ie, CPULM32State),
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VMSTATE_UINT32(icc, CPULM32State),
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VMSTATE_UINT32(dcc, CPULM32State),
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VMSTATE_UINT32(cc, CPULM32State),
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VMSTATE_UINT32(eba, CPULM32State),
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VMSTATE_UINT32(dc, CPULM32State),
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VMSTATE_UINT32(deba, CPULM32State),
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VMSTATE_UINT32_ARRAY(bp, CPULM32State, 4),
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VMSTATE_UINT32_ARRAY(wp, CPULM32State, 4),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -75,11 +75,11 @@ uint32_t helper_rcsr_jrx(void)
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
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void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
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void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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CPULM32State *saved_env;
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unsigned long pc;
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int ret;
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@ -64,7 +64,7 @@ enum {
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/* This is the state at translation time. */
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typedef struct DisasContext {
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CPUState *env;
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CPULM32State *env;
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target_ulong pc;
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/* Decoder. */
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@ -987,7 +987,7 @@ static inline void decode(DisasContext *dc)
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decinfo[dc->opcode](dc);
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}
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static void check_breakpoint(CPUState *env, DisasContext *dc)
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static void check_breakpoint(CPULM32State *env, DisasContext *dc)
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{
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CPUBreakpoint *bp;
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@ -1003,7 +1003,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
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}
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/* generate intermediate code for basic block 'tb'. */
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static void gen_intermediate_code_internal(CPUState *env,
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static void gen_intermediate_code_internal(CPULM32State *env,
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TranslationBlock *tb, int search_pc)
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{
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struct DisasContext ctx, *dc = &ctx;
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@ -1129,17 +1129,17 @@ static void gen_intermediate_code_internal(CPUState *env,
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#endif
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}
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void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(env, tb, 0);
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}
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void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb)
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void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(env, tb, 1);
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}
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void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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int i;
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@ -1171,7 +1171,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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cpu_fprintf(f, "\n\n");
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}
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void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
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void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
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{
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env->pc = gen_opc_pc[pc_pos];
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}
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@ -1184,48 +1184,48 @@ void lm32_translate_init(void)
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for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
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cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, regs[i]),
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offsetof(CPULM32State, regs[i]),
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regnames[i]);
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}
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for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
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cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, bp[i]),
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offsetof(CPULM32State, bp[i]),
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regnames[32+i]);
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}
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for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
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cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, wp[i]),
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offsetof(CPULM32State, wp[i]),
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regnames[36+i]);
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}
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cpu_pc = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, pc),
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offsetof(CPULM32State, pc),
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"pc");
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cpu_ie = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, ie),
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offsetof(CPULM32State, ie),
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"ie");
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cpu_icc = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, icc),
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offsetof(CPULM32State, icc),
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"icc");
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cpu_dcc = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, dcc),
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offsetof(CPULM32State, dcc),
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"dcc");
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cpu_cc = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, cc),
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offsetof(CPULM32State, cc),
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"cc");
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cpu_cfg = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, cfg),
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offsetof(CPULM32State, cfg),
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"cfg");
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cpu_eba = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, eba),
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offsetof(CPULM32State, eba),
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"eba");
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cpu_dc = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, dc),
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offsetof(CPULM32State, dc),
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"dc");
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cpu_deba = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUState, deba),
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offsetof(CPULM32State, deba),
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"deba");
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}
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