target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin <ake@igel.co.jp> Message-id: 20221101064250.12444-1-ake@igel.co.jp Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3501,19 +3501,22 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
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ARMMMUIdx mmu_idx;
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int secure = arm_is_secure_below_el3(env);
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uint64_t hcr_el2 = arm_hcr_el2_eff(env);
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bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
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switch (ri->opc2 & 6) {
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case 0:
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switch (ri->opc1) {
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case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
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if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
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mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
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mmu_idx = regime_e20 ?
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ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN;
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} else {
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mmu_idx = ARMMMUIdx_Stage1_E1;
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mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1;
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}
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break;
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case 4: /* AT S1E2R, AT S1E2W */
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mmu_idx = ARMMMUIdx_E2;
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mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2;
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break;
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case 6: /* AT S1E3R, AT S1E3W */
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mmu_idx = ARMMMUIdx_E3;
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@ -3524,13 +3527,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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break;
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case 2: /* AT S1E0R, AT S1E0W */
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mmu_idx = ARMMMUIdx_Stage1_E0;
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mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0;
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break;
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case 4: /* AT S12E1R, AT S12E1W */
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mmu_idx = ARMMMUIdx_E10_1;
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mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1;
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break;
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case 6: /* AT S12E0R, AT S12E0W */
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mmu_idx = ARMMMUIdx_E10_0;
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mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0;
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break;
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default:
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g_assert_not_reached();
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