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pull-loongarch-20240912

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-----BEGIN PGP SIGNATURE-----
 
 iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZuLmLgAKCRBAov/yOSY+
 38JNA/9UdorT4a7H+H5PhNeEu2EHDgMPb7+gxyYKw03mOG2MB3KFzkK0LRQShaPt
 ADJmIqAFlc9SJLkbo6ELMDl+ZnUU9OdC/P6YU5iBG71zx1PonMwuyJTWhlBwxWcG
 +OB8aDBUALoe/Gb4za152I84cR08g58TgLnXNfEkCM8lnPfAug==
 =Plwu
 -----END PGP SIGNATURE-----

Merge tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20240912

# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZuLmLgAKCRBAov/yOSY+
# 38JNA/9UdorT4a7H+H5PhNeEu2EHDgMPb7+gxyYKw03mOG2MB3KFzkK0LRQShaPt
# ADJmIqAFlc9SJLkbo6ELMDl+ZnUU9OdC/P6YU5iBG71zx1PonMwuyJTWhlBwxWcG
# +OB8aDBUALoe/Gb4za152I84cR08g58TgLnXNfEkCM8lnPfAug==
# =Plwu
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 12 Sep 2024 14:01:34 BST
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu:
  hw/loongarch: Add acpi SPCR table support
  hw/loongarch: virt: pass random seed to fdt
  hw/loongarch: virt: support up to 4 serial ports
  target/loongarch: Support QMP dump-guest-memory
  target/loongarch/kvm: Add vCPU reset function
  hw/loongarch: Remove default enable with VIRTIO_VGA device
  target/loongarch: Add compatible support about VM reboot

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-09-13 11:38:15 +01:00
commit 63731c346f
10 changed files with 273 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/loongarch/Kconfig
View File

@ -5,7 +5,6 @@ config LOONGARCH_VIRT
select DEVICE_TREE
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE
imply VIRTIO_VGA
imply PCI_DEVICES
imply NVDIMM
imply TPM_TIS_SYSBUS

61
hw/loongarch/acpi-build.c
View File

@ -31,6 +31,7 @@
#include "hw/acpi/generic_event_device.h"
#include "hw/pci-host/gpex.h"
#include "sysemu/sysemu.h"
#include "sysemu/tpm.h"
#include "hw/platform-bus.h"
#include "hw/acpi/aml-build.h"
@ -241,6 +242,44 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
acpi_table_end(linker, &table);
}
/*
* Serial Port Console Redirection Table (SPCR)
* https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
*/
static void
spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine)
{
LoongArchVirtMachineState *lvms;
AcpiSpcrData serial = {
.interface_type = 0, /* 16550 compatible */
.base_addr.id = AML_AS_SYSTEM_MEMORY,
.base_addr.width = 32,
.base_addr.offset = 0,
.base_addr.size = 1,
.base_addr.addr = VIRT_UART_BASE,
.interrupt_type = 0, /* Interrupt not supported */
.pc_interrupt = 0,
.interrupt = VIRT_UART_IRQ,
.baud_rate = 7, /* 115200 */
.parity = 0,
.stop_bits = 1,
.flow_control = 0,
.terminal_type = 3, /* ANSI */
.language = 0, /* Language */
.pci_device_id = 0xffff, /* not a PCI device*/
.pci_vendor_id = 0xffff, /* not a PCI device*/
.pci_bus = 0,
.pci_device = 0,
.pci_function = 0,
.pci_flags = 0,
.pci_segment = 0,
};
lvms = LOONGARCH_VIRT_MACHINE(machine);
build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
lvms->oem_table_id);
}
typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
@ -252,23 +291,27 @@ struct AcpiBuildState {
MemoryRegion *linker_mr;
} AcpiBuildState;
static void build_uart_device_aml(Aml *table)
static void build_uart_device_aml(Aml *table, int index)
{
Aml *dev;
Aml *crs;
Aml *pkg0, *pkg1, *pkg2;
uint32_t uart_irq = VIRT_UART_IRQ;
Aml *scope;
uint32_t uart_irq;
uint64_t base;
Aml *scope = aml_scope("_SB");
dev = aml_device("COMA");
uart_irq = VIRT_UART_IRQ + index;
base = VIRT_UART_BASE + index * VIRT_UART_SIZE;
scope = aml_scope("_SB");
dev = aml_device("COM%d", index);
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
aml_append(dev, aml_name_decl("_UID", aml_int(index)));
aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
crs = aml_resource_template();
aml_append(crs,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE,
0, VIRT_UART_BASE, VIRT_UART_BASE + VIRT_UART_SIZE - 1,
0, base, base + VIRT_UART_SIZE - 1,
0, VIRT_UART_SIZE));
aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
AML_SHARED, &uart_irq, 1));
@ -401,6 +444,7 @@ static void acpi_dsdt_add_tpm(Aml *scope, LoongArchVirtMachineState *vms)
static void
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
{
int i;
Aml *dsdt, *scope, *pkg;
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lvms->oem_id,
@ -408,7 +452,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
build_uart_device_aml(dsdt);
for (i = 0; i < VIRT_UART_COUNT; i++)
build_uart_device_aml(dsdt, i);
build_pci_device_aml(dsdt, lvms);
build_la_ged_aml(dsdt, machine);
build_flash_aml(dsdt, lvms);
@ -477,6 +522,8 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, machine);
acpi_add_table(table_offsets, tables_blob);
spcr_setup(tables_blob, tables->linker, machine);
if (machine->numa_state->num_nodes) {
if (machine->numa_state->have_numa_distance) {

33
hw/loongarch/virt.c
View File

@ -48,6 +48,7 @@
#include "hw/block/flash.h"
#include "hw/virtio/virtio-iommu.h"
#include "qemu/error-report.h"
#include "qemu/guest-random.h"
static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms)
{
@ -280,10 +281,10 @@ static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms,
}
static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
uint32_t *pch_pic_phandle)
uint32_t *pch_pic_phandle, hwaddr base,
int irq, bool chosen)
{
char *nodename;
hwaddr base = VIRT_UART_BASE;
hwaddr size = VIRT_UART_SIZE;
MachineState *ms = MACHINE(lvms);
@ -292,9 +293,9 @@ static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4);
if (chosen)
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*pch_pic_phandle);
g_free(nodename);
@ -303,6 +304,7 @@ static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
static void create_fdt(LoongArchVirtMachineState *lvms)
{
MachineState *ms = MACHINE(lvms);
uint8_t rng_seed[32];
ms->fdt = create_device_tree(&lvms->fdt_size);
if (!ms->fdt) {
@ -316,6 +318,10 @@ static void create_fdt(LoongArchVirtMachineState *lvms)
qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
qemu_fdt_add_subnode(ms->fdt, "/chosen");
/* Pass seed to RNG */
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
}
static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
@ -706,11 +712,18 @@ static void virt_devices_init(DeviceState *pch_pic,
/* Add pcie node */
fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
qdev_get_gpio_in(pch_pic,
VIRT_UART_IRQ - VIRT_GSI_BASE),
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
fdt_add_uart_node(lvms, pch_pic_phandle);
/*
* Create uart fdt node in reverse order so that they appear
* in the finished device tree lowest address first
*/
for (i = VIRT_UART_COUNT; i --> 0;) {
hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
serial_mm_init(get_system_memory(), base, 0,
qdev_get_gpio_in(pch_pic, irq),
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
}
/* Network init */
pci_init_nic_devices(pci_bus, mc->default_nic);

9
include/hw/pci-host/ls7a.h
View File

@ -36,17 +36,18 @@
#define VIRT_PCH_PIC_IRQ_NUM 32
#define VIRT_GSI_BASE 64
#define VIRT_DEVICE_IRQS 16
#define VIRT_UART_COUNT 4
#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
#define VIRT_UART_BASE 0x1fe001e0
#define VIRT_UART_SIZE 0X100
#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 3)
#define VIRT_UART_SIZE 0x100
#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
#define VIRT_RTC_LEN 0x100
#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 4)
#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
#define VIRT_PLATFORM_BUS_SIZE 0x2000000
#define VIRT_PLATFORM_BUS_NUM_IRQS 2
#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 5)
#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
#endif

167
target/loongarch/arch_dump.c Normal file
View File

@ -0,0 +1,167 @@
/*
* Support for writing ELF notes for LoongArch architectures
*
* Copyright (c) 2023 Loongarch Technology
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "elf.h"
#include "sysemu/dump.h"
#include "internals.h"
/* struct user_pt_regs from arch/loongarch/include/uapi/asm/ptrace.h */
struct loongarch_user_regs {
uint64_t gpr[32];
uint64_t pad1[1];
/* Special CSR registers. */
uint64_t csr_era;
uint64_t csr_badv;
uint64_t pad2[10];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct loongarch_user_regs) != 360);
/* struct elf_prstatus from include/uapi/linux/elfcore.h */
struct loongarch_elf_prstatus {
char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */
uint32_t pr_pid;
/*
* 76 == offsetof(struct elf_prstatus, pr_reg) -
* offsetof(struct elf_prstatus, pr_ppid)
*/
char pad2[76];
struct loongarch_user_regs pr_reg;
uint32_t pr_fpvalid;
char pad3[4];
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct loongarch_elf_prstatus) != 480);
/* struct user_fp_state from arch/loongarch/include/uapi/asm/ptrace.h */
struct loongarch_fpu_struct {
uint64_t fpr[32];
uint64_t fcc;
unsigned int fcsr;
} QEMU_PACKED;
QEMU_BUILD_BUG_ON(sizeof(struct loongarch_fpu_struct) != 268);
struct loongarch_note {
Elf64_Nhdr hdr;
char name[8]; /* align_up(sizeof("CORE"), 4) */
union {
struct loongarch_elf_prstatus prstatus;
struct loongarch_fpu_struct fpu;
};
} QEMU_PACKED;
#define LOONGARCH_NOTE_HEADER_SIZE offsetof(struct loongarch_note, prstatus)
#define LOONGARCH_PRSTATUS_NOTE_SIZE \
(LOONGARCH_NOTE_HEADER_SIZE + sizeof(struct loongarch_elf_prstatus))
#define LOONGARCH_PRFPREG_NOTE_SIZE \
(LOONGARCH_NOTE_HEADER_SIZE + sizeof(struct loongarch_fpu_struct))
static void loongarch_note_init(struct loongarch_note *note, DumpState *s,
const char *name, Elf64_Word namesz,
Elf64_Word type, Elf64_Word descsz)
{
memset(note, 0, sizeof(*note));
note->hdr.n_namesz = cpu_to_dump32(s, namesz);
note->hdr.n_descsz = cpu_to_dump32(s, descsz);
note->hdr.n_type = cpu_to_dump32(s, type);
memcpy(note->name, name, namesz);
}
static int loongarch_write_elf64_fprpreg(WriteCoreDumpFunction f,
CPULoongArchState *env, int cpuid,
DumpState *s)
{
struct loongarch_note note;
int ret, i;
loongarch_note_init(&note, s, "CORE", 5, NT_PRFPREG, sizeof(note.fpu));
note.fpu.fcsr = cpu_to_dump64(s, env->fcsr0);
for (i = 0; i < 8; i++) {
note.fpu.fcc |= env->cf[i] << (8 * i);
}
note.fpu.fcc = cpu_to_dump64(s, note.fpu.fcc);
for (i = 0; i < 32; ++i) {
note.fpu.fpr[i] = cpu_to_dump64(s, env->fpr[i].vreg.UD[0]);
}
ret = f(&note, LOONGARCH_PRFPREG_NOTE_SIZE, s);
if (ret < 0) {
return -1;
}
return 0;
}
int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s)
{
struct loongarch_note note;
CPULoongArchState *env = &LOONGARCH_CPU(cs)->env;
int ret, i;
loongarch_note_init(&note, s, "CORE", 5, NT_PRSTATUS,
sizeof(note.prstatus));
note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
note.prstatus.pr_fpvalid = cpu_to_dump32(s, 1);
for (i = 0; i < 32; ++i) {
note.prstatus.pr_reg.gpr[i] = cpu_to_dump64(s, env->gpr[i]);
}
note.prstatus.pr_reg.csr_era = cpu_to_dump64(s, env->CSR_ERA);
note.prstatus.pr_reg.csr_badv = cpu_to_dump64(s, env->CSR_BADV);
ret = f(&note, LOONGARCH_PRSTATUS_NOTE_SIZE, s);
if (ret < 0) {
return -1;
}
ret = loongarch_write_elf64_fprpreg(f, env, cpuid, s);
if (ret < 0) {
return -1;
}
return ret;
}
int cpu_get_dump_info(ArchDumpInfo *info,
const GuestPhysBlockList *guest_phys_blocks)
{
info->d_machine = EM_LOONGARCH;
info->d_endian = ELFDATA2LSB;
info->d_class = ELFCLASS64;
return 0;
}
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
size_t note_size = 0;
if (class == ELFCLASS64) {
note_size = LOONGARCH_PRSTATUS_NOTE_SIZE + LOONGARCH_PRFPREG_NOTE_SIZE;
}
return note_size * nr_cpus;
}

17
target/loongarch/cpu.c
View File

@ -549,6 +549,20 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
env->CSR_TID = cs->cpu_index;
/*
* Workaround for edk2-stable202408, CSR PGD register is set only if
* its value is equal to zero for boot cpu, it causes reboot issue.
*
* Here clear CSR registers relative with TLB.
*/
env->CSR_PGDH = 0;
env->CSR_PGDL = 0;
env->CSR_PWCL = 0;
env->CSR_PWCH = 0;
env->CSR_STLBPS = 0;
env->CSR_EENTRY = 0;
env->CSR_TLBRENTRY = 0;
env->CSR_MERRENTRY = 0;
for (n = 0; n < 4; n++) {
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
@ -563,7 +577,7 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
memset(env->tlb, 0, sizeof(env->tlb));
#endif
if (kvm_enabled()) {
kvm_arch_reset_vcpu(env);
kvm_arch_reset_vcpu(cs);
}
#endif
@ -754,6 +768,7 @@ static const TCGCPUOps loongarch_tcg_ops = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps loongarch_sysemu_ops = {
.write_elf64_note = loongarch_cpu_write_elf64_note,
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
};

2
target/loongarch/internals.h
View File

@ -72,5 +72,7 @@ void write_fcc(CPULoongArchState *env, uint64_t val);
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, DumpState *s);
#endif

5
target/loongarch/kvm/kvm.c
View File

@ -476,9 +476,12 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs)
return ret;
}
void kvm_arch_reset_vcpu(CPULoongArchState *env)
void kvm_arch_reset_vcpu(CPUState *cs)
{
CPULoongArchState *env = cpu_env(cs);
env->mp_state = KVM_MP_STATE_RUNNABLE;
kvm_set_one_reg(cs, KVM_REG_LOONGARCH_VCPU_RESET, 0);
}
static int kvm_loongarch_get_mpstate(CPUState *cs)

2
target/loongarch/kvm/kvm_loongarch.h
View File

@ -11,6 +11,6 @@
#define QEMU_KVM_LOONGARCH_H
int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
void kvm_arch_reset_vcpu(CPULoongArchState *env);
void kvm_arch_reset_vcpu(CPUState *cs);
#endif

1
target/loongarch/meson.build
View File

@ -8,6 +8,7 @@ loongarch_ss.add(files(
loongarch_system_ss = ss.source_set()
loongarch_system_ss.add(files(
'arch_dump.c',
'cpu_helper.c',
'loongarch-qmp-cmds.c',
'machine.c',