target/mips: Add reset state for PWSize and PWField registers
Add reset state for PWSize and PWField registers. The reset state is different for pre-R6 and R6 (and post-R6) ISAa. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -26444,6 +26444,24 @@ void cpu_state_reset(CPUMIPSState *env)
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env->CP0_Status |= (1 << CP0St_FR);
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}
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if (env->insn_flags & ISA_MIPS32R6) {
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/* PTW = 1 */
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env->CP0_PWSize = 0x40;
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/* GDI = 12 */
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/* UDI = 12 */
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/* MDI = 12 */
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/* PRI = 12 */
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/* PTEI = 2 */
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env->CP0_PWField = 0x0C30C302;
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} else {
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/* GDI = 0 */
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/* UDI = 0 */
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/* MDI = 0 */
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/* PRI = 0 */
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/* PTEI = 2 */
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env->CP0_PWField = 0x02;
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}
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if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
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/* microMIPS on reset when Config3.ISA is 3 */
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env->hflags |= MIPS_HFLAG_M16;
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